AC_RANGE_CHECK/DRAGONFLY Simulation Results

Saturday June 06 2026 03:15:30 UTC

GitHub Revision: `285e653a0b`

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	ac_range_check_smoke	ac_range_check_smoke	27.370s	1.527ms	19	20	95.00
V1	ac_range_check_smoke_racl	ac_range_check_smoke_racl	33.990s	36.727ms	20	20	100.00
V1	csr_hw_reset	ac_range_check_csr_hw_reset	1.340s	82.684us	5	5	100.00
V1	csr_rw	ac_range_check_csr_rw	1.400s	53.215us	20	20	100.00
V1	csr_bit_bash	ac_range_check_csr_bit_bash	25.040s	6.857ms	5	5	100.00
V1	csr_aliasing	ac_range_check_csr_aliasing	16.790s	5.947ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	ac_range_check_csr_mem_rw_with_rand_reset	1.720s	90.037us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	ac_range_check_csr_rw	1.400s	53.215us	20	20	100.00
		ac_range_check_csr_aliasing	16.790s	5.947ms	5	5	100.00
V1		TOTAL			94	95	98.95
V2	ac_range_check_lock_range	ac_range_check_lock_range	1.940s	236.585us	20	20	100.00
V2	ac_range_bypass_enable	ac_range_check_bypass	18.020s	5.694ms	1	1	100.00
V2	stress_all	ac_range_check_stress_all	2.496m	27.730ms	44	50	88.00
V2	alert_test	ac_range_check_alert_test	0.860s	16.278us	50	50	100.00
V2	intr_test	ac_range_check_intr_test	0.810s	12.770us	50	50	100.00
V2	tl_d_oob_addr_access	ac_range_check_tl_errors	2.790s	143.181us	20	20	100.00
V2	tl_d_illegal_access	ac_range_check_tl_errors	2.790s	143.181us	20	20	100.00
V2	tl_d_outstanding_access	ac_range_check_csr_hw_reset	1.340s	82.684us	5	5	100.00
		ac_range_check_csr_rw	1.400s	53.215us	20	20	100.00
		ac_range_check_csr_aliasing	16.790s	5.947ms	5	5	100.00
		ac_range_check_same_csr_outstanding	3.610s	803.737us	20	20	100.00
V2	tl_d_partial_access	ac_range_check_csr_hw_reset	1.340s	82.684us	5	5	100.00
		ac_range_check_csr_rw	1.400s	53.215us	20	20	100.00
		ac_range_check_csr_aliasing	16.790s	5.947ms	5	5	100.00
		ac_range_check_same_csr_outstanding	3.610s	803.737us	20	20	100.00
V2		TOTAL			205	211	97.16
V2S	shadow_reg_update_error	ac_range_check_shadow_reg_errors	15.120s	12.853ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	ac_range_check_shadow_reg_errors	15.120s	12.853ms	20	20	100.00
V2S	shadow_reg_storage_error	ac_range_check_shadow_reg_errors	15.120s	12.853ms	20	20	100.00
V2S	shadowed_reset_glitch	ac_range_check_shadow_reg_errors	15.120s	12.853ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	ac_range_check_shadow_reg_errors_with_csr_rw	1.115m	5.299ms	20	20	100.00
V2S	tl_intg_err	ac_range_check_sec_cm	0.790s	13.445us	5	5	100.00
		ac_range_check_tl_intg_err	6.990s	1.753ms	20	20	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	ac_range_check_stress_all_with_rand_reset	4.450m	2.096ms	50	50	100.00
V3		TOTAL			50	50	100.00
	Unmapped tests	ac_range_check_smoke_high_threshold	18.580s	4.338ms	20	20	100.00
		ac_range_check_rst_safe_smoke	4.592m	100.051ms	17	20	85.00
		TOTAL			451	461	97.83

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	2	2	1	50.00
V1	7	7	6	85.71
V2	7	7	6	85.71
V2S	4	4	4	100.00
V3	1	1	1	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.43	99.87	98.33	83.44	--	99.55	97.75	81.61

Failure Buckets

UVM_ERROR (ac_range_check_scoreboard.sv:373) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: ac_range_check_reg_block.intr_state has 6 failures:
- Test ac_range_check_stress_all has 5 failures.
  - 9.ac_range_check_stress_all.10368882584646398910159766518769909961975709291454599455335384638823785813941
    Line 8541, in log /home/runner/_work/pavona/pavona/scratch/main/ac_range_check_top_dragonfly-sim-vcs/9.ac_range_check_stress_all/latest/run.log
```
  UVM_ERROR @ 7937416438 ps: (ac_range_check_scoreboard.sv:373) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
  UVM_INFO @ 7937416438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 16.ac_range_check_stress_all.76647935368570861007134273491469022021520389715128755652169300350158081548769
    Line 21864, in log /home/runner/_work/pavona/pavona/scratch/main/ac_range_check_top_dragonfly-sim-vcs/16.ac_range_check_stress_all/latest/run.log
```
  UVM_ERROR @ 8691997793 ps: (ac_range_check_scoreboard.sv:373) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
  UVM_INFO @ 8691997793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
- Test ac_range_check_smoke has 1 failures.
  - 11.ac_range_check_smoke.48880396257335081480467662580509232878104488412304866370904747790112927348539
    Line 4243, in log /home/runner/_work/pavona/pavona/scratch/main/ac_range_check_top_dragonfly-sim-vcs/11.ac_range_check_smoke/latest/run.log
```
  UVM_ERROR @ 1122381876 ps: (ac_range_check_scoreboard.sv:373) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
  UVM_INFO @ 1122381876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Offending '(pend_req[h2d.a_source].pend == *)' has 3 failures:

Test ac_range_check_rst_safe_smoke has 3 failures.

3.ac_range_check_rst_safe_smoke.9036902921185600458861824498522370797473496632198008891106946622569083125823
Line 4335, in log /home/runner/_work/pavona/pavona/scratch/main/ac_range_check_top_dragonfly-sim-vcs/3.ac_range_check_rst_safe_smoke/latest/run.log

      Offending '(pend_req[h2d.a_source].pend == 0)'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 284: tb.dut.tlul_assert_device.gen_device.gen_h2d.pendingReqPerSrc_M: started at 7390562794ps failed at 7390562794ps
      Offending '(pend_req[h2d.a_source].pend == 0)'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 284: tb.dut.tlul_assert_device.gen_device.gen_h2d.pendingReqPerSrc_M: started at 7390896128ps failed at 7390896128ps
      Offending '(pend_req[h2d.a_source].pend == 0)'

11.ac_range_check_rst_safe_smoke.92220468047865315637146347523290963300274735744044915435133818950116075841207
Line 4953, in log /home/runner/_work/pavona/pavona/scratch/main/ac_range_check_top_dragonfly-sim-vcs/11.ac_range_check_rst_safe_smoke/latest/run.log

      Offending '(pend_req[h2d.a_source].pend == 0)'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 284: tb.dut.tlul_assert_device.gen_device.gen_h2d.pendingReqPerSrc_M: started at 3657902502ps failed at 3657902502ps
      Offending '(pend_req[h2d.a_source].pend == 0)'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 284: tb.dut.tlul_assert_device.gen_device.gen_h2d.pendingReqPerSrc_M: started at 3658069168ps failed at 3658069168ps
      Offending '(pend_req[h2d.a_source].pend == 0)'

... and 1 more failures.

UVM_ERROR (ac_range_check_scoreboard.sv:166) [scoreboard] Unable to get any item from tl_unfilt_d_chan_fifo. has 1 failures:
- Test ac_range_check_stress_all has 1 failures.
  - 18.ac_range_check_stress_all.97154932270960306197671005021995092738746694198949796945548896132962006364933
    Line 20183, in log /home/runner/_work/pavona/pavona/scratch/main/ac_range_check_top_dragonfly-sim-vcs/18.ac_range_check_stress_all/latest/run.log
```
  UVM_ERROR @ 100277678728 ps: (ac_range_check_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Unable to get any item from tl_unfilt_d_chan_fifo.
  UVM_INFO @ 100277678728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```