ACC/STANDARD Simulation Results

Saturday June 06 2026 03:15:30 UTC

GitHub Revision: 285e653a0b

Branch: main

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke acc_smoke 11.142s 0 1 0.00
V1 single_binary acc_single 11.143s 0 100 0.00
V1 csr_hw_reset acc_csr_hw_reset 1.620s 23.161us 5 5 100.00
V1 csr_rw acc_csr_rw 1.540s 18.954us 20 20 100.00
V1 csr_bit_bash acc_csr_bit_bash 2.510s 215.182us 3 3 100.00
V1 csr_aliasing acc_csr_aliasing 1.490s 15.758us 5 5 100.00
V1 csr_mem_rw_with_rand_reset acc_csr_mem_rw_with_rand_reset 3.500s 70.741us 4 4 100.00
V1 regwen_csr_and_corresponding_lockable_csr acc_csr_rw 1.540s 18.954us 20 20 100.00
acc_csr_aliasing 1.490s 15.758us 5 5 100.00
V1 mem_walk acc_mem_walk 2.798m 10.502ms 5 5 100.00
V1 mem_partial_access acc_mem_partial_access 59.260s 7.906ms 5 5 100.00
V1 TOTAL 47 148 31.76
V2 reset_recovery acc_reset 10.125s 0 10 0.00
V2 multi_error acc_multi_err 11.135s 0 1 0.00
V2 back_to_back acc_multi 12.154s 0 10 0.00
V2 stress_all acc_stress_all 8.056s 0 10 0.00
V2 lc_escalation acc_escalate 8.095s 0 60 0.00
V2 zero_state_err_urnd acc_zero_state_err_urnd 7.050s 0 5 0.00
V2 sw_errs_fatal_chk acc_sw_errs_fatal_chk 6.034s 0 10 0.00
V2 alert_test acc_alert_test 1.010s 26.383us 3 3 100.00
V2 intr_test acc_intr_test 1.390s 52.161us 3 3 100.00
V2 tl_d_oob_addr_access acc_tl_errors 3.230s 100.793us 3 3 100.00
V2 tl_d_illegal_access acc_tl_errors 3.230s 100.793us 3 3 100.00
V2 tl_d_outstanding_access acc_csr_hw_reset 1.620s 23.161us 5 5 100.00
acc_csr_rw 1.540s 18.954us 20 20 100.00
acc_csr_aliasing 1.490s 15.758us 5 5 100.00
acc_same_csr_outstanding 2.010s 34.259us 20 20 100.00
V2 tl_d_partial_access acc_csr_hw_reset 1.620s 23.161us 5 5 100.00
acc_csr_rw 1.540s 18.954us 20 20 100.00
acc_csr_aliasing 1.490s 15.758us 5 5 100.00
acc_same_csr_outstanding 2.010s 34.259us 20 20 100.00
V2 TOTAL 29 135 21.48
V2S mem_integrity acc_imem_err 9.113s 0 10 0.00
acc_dmem_err 9.109s 0 15 0.00
V2S internal_integrity acc_alu_bignum_mod_err 8.056s 0 5 0.00
acc_controller_ispr_rdata_err 8.055s 0 5 0.00
acc_mac_bignum_acc_err 8.055s 0 5 0.00
acc_urnd_err 3.089s 0 2 0.00
V2S kmac_error acc_kmac_err 0 0 --
V2S illegal_bus_access acc_illegal_mem_acc 6.034s 0 5 0.00
V2S acc_mem_gnt_acc_err acc_mem_gnt_acc_err 1.033s 0 2 0.00
V2S acc_non_sec_partial_wipe acc_partial_wipe 3.108s 0 10 0.00
V2S tl_intg_err acc_sec_cm 1.992m 2.215ms 8 8 100.00
acc_tl_intg_err 7.900s 600.127us 7 7 100.00
V2S passthru_mem_tl_intg_err acc_passthru_mem_tl_intg_err 33.400s 1.330ms 5 5 100.00
V2S prim_fsm_check acc_sec_cm 1.992m 2.215ms 8 8 100.00
V2S prim_count_check acc_sec_cm 1.992m 2.215ms 8 8 100.00
V2S sec_cm_mem_scramble acc_smoke 11.142s 0 1 0.00
V2S sec_cm_data_mem_integrity acc_dmem_err 9.109s 0 15 0.00
V2S sec_cm_instruction_mem_integrity acc_imem_err 9.113s 0 10 0.00
V2S sec_cm_bus_integrity acc_tl_intg_err 7.900s 600.127us 7 7 100.00
V2S sec_cm_controller_fsm_global_esc acc_escalate 8.095s 0 60 0.00
V2S sec_cm_controller_fsm_local_esc acc_imem_err 9.113s 0 10 0.00
acc_dmem_err 9.109s 0 15 0.00
acc_zero_state_err_urnd 7.050s 0 5 0.00
acc_illegal_mem_acc 6.034s 0 5 0.00
acc_sec_cm 1.992m 2.215ms 8 8 100.00
V2S sec_cm_controller_fsm_sparse acc_sec_cm 1.992m 2.215ms 8 8 100.00
V2S sec_cm_scramble_key_sideload acc_single 11.143s 0 100 0.00
V2S sec_cm_scramble_ctrl_fsm_local_esc acc_imem_err 9.113s 0 10 0.00
acc_dmem_err 9.109s 0 15 0.00
acc_zero_state_err_urnd 7.050s 0 5 0.00
acc_illegal_mem_acc 6.034s 0 5 0.00
acc_sec_cm 1.992m 2.215ms 8 8 100.00
V2S sec_cm_scramble_ctrl_fsm_sparse acc_sec_cm 1.992m 2.215ms 8 8 100.00
V2S sec_cm_start_stop_ctrl_fsm_global_esc acc_escalate 8.095s 0 60 0.00
V2S sec_cm_start_stop_ctrl_fsm_local_esc acc_imem_err 9.113s 0 10 0.00
acc_dmem_err 9.109s 0 15 0.00
acc_zero_state_err_urnd 7.050s 0 5 0.00
acc_illegal_mem_acc 6.034s 0 5 0.00
acc_sec_cm 1.992m 2.215ms 8 8 100.00
V2S sec_cm_start_stop_ctrl_fsm_sparse acc_sec_cm 1.992m 2.215ms 8 8 100.00
V2S sec_cm_data_reg_sw_sca acc_single 11.143s 0 100 0.00
V2S sec_cm_ctrl_redun acc_ctrl_redun 3.110s 0 12 0.00
V2S sec_cm_pc_ctrl_flow_redun acc_pc_ctrl_flow_redun 6.035s 0 5 0.00
V2S sec_cm_rnd_bus_consistency acc_rnd_sec_cm 2.061s 0 5 0.00
V2S sec_cm_rnd_rng_digest acc_rnd_sec_cm 2.061s 0 5 0.00
V2S sec_cm_rf_base_data_reg_sw_integrity acc_rf_base_intg_err 8.056s 0 10 0.00
V2S sec_cm_rf_base_data_reg_sw_glitch_detect acc_sec_cm 1.992m 2.215ms 8 8 100.00
V2S sec_cm_stack_wr_ptr_ctr_redun acc_sec_cm 1.992m 2.215ms 8 8 100.00
V2S sec_cm_rf_bignum_data_reg_sw_integrity acc_rf_bignum_intg_err 8.055s 0 10 0.00
V2S sec_cm_rf_bignum_data_reg_sw_glitch_detect acc_sec_cm 1.992m 2.215ms 8 8 100.00
V2S sec_cm_loop_stack_ctr_redun acc_sec_cm 1.992m 2.215ms 8 8 100.00
V2S sec_cm_loop_stack_addr_integrity acc_stack_addr_integ_chk 3.108s 0 5 0.00
V2S sec_cm_call_stack_addr_integrity acc_stack_addr_integ_chk 3.108s 0 5 0.00
V2S sec_cm_start_stop_ctrl_state_consistency acc_sec_wipe_err 4.104s 0 7 0.00
V2S sec_cm_data_mem_sec_wipe acc_single 11.143s 0 100 0.00
V2S sec_cm_instruction_mem_sec_wipe acc_single 11.143s 0 100 0.00
V2S sec_cm_data_reg_sw_sec_wipe acc_single 11.143s 0 100 0.00
V2S sec_cm_write_mem_integrity acc_multi 12.154s 0 10 0.00
V2S sec_cm_ctrl_flow_count acc_single 11.143s 0 100 0.00
V2S sec_cm_ctrl_flow_sca acc_single 11.143s 0 100 0.00
V2S sec_cm_data_mem_sw_noaccess acc_sw_no_acc 2.060s 0 5 0.00
V2S sec_cm_key_sideload acc_single 11.143s 0 100 0.00
V2S sec_cm_tlul_fifo_ctr_redun acc_sec_cm 1.992m 2.215ms 8 8 100.00
V2S TOTAL 20 138 14.49
V3 stress_all_with_rand_reset acc_stress_all_with_rand_reset 8.056s 0 10 0.00
V3 TOTAL 0 10 0.00
TOTAL 96 431 22.27

Testplan Progress

Items Total Written Passing Progress
V1 9 9 7 77.78
V2 11 11 4 36.36
V2S 21 20 3 14.29
V3 1 1 0 0.00

Coverage Results

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
49.76 87.84 33.21 52.26 31.25 66.23 76.82 0.71

Failure Buckets