ADC_CTRL Simulation Results

Saturday June 06 2026 03:15:30 UTC

GitHub Revision: 285e653a0b

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	2.180s	5.939ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.000s	1.050ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.630s	540.753us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.718m	52.463ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	3.520s	920.557us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	1.480s	554.687us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.630s	540.753us	20	20	100.00
		adc_ctrl_csr_aliasing	3.520s	920.557us	5	5	100.00
V1		TOTAL			56	56	100.00
V2	filters_polled	adc_ctrl_filters_polled	9.389m	325.639ms	4	4	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	33.210s	336.740ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	8.055m	327.523ms	8	8	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	1.210m	164.277ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	14.431m	537.841ms	18	18	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	8.188m	402.867ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	12.574m	490.621ms	26	26	100.00
V2	clock_gating	adc_ctrl_clock_gating	12.424m	542.879ms	11	12	91.67
V2	poweron_counter	adc_ctrl_poweron_counter	6.290s	4.536ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	36.710s	42.745ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	2.916m	108.130ms	8	8	100.00
V2	stress_all	adc_ctrl_stress_all	21.349m	10.000s	19	20	95.00
V2	alert_test	adc_ctrl_alert_test	1.780s	495.152us	3	3	100.00
V2	intr_test	adc_ctrl_intr_test	1.440s	489.723us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	2.130s	447.309us	5	5	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	2.130s	447.309us	5	5	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.000s	1.050ms	5	5	100.00
		adc_ctrl_csr_rw	1.630s	540.753us	20	20	100.00
		adc_ctrl_csr_aliasing	3.520s	920.557us	5	5	100.00
		adc_ctrl_same_csr_outstanding	8.270s	4.286ms	3	3	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.000s	1.050ms	5	5	100.00
		adc_ctrl_csr_rw	1.630s	540.753us	20	20	100.00
		adc_ctrl_csr_aliasing	3.520s	920.557us	5	5	100.00
		adc_ctrl_same_csr_outstanding	8.270s	4.286ms	3	3	100.00
V2		TOTAL			160	162	98.77
V2S	tl_intg_err	adc_ctrl_sec_cm	13.650s	8.064ms	3	3	100.00
		adc_ctrl_tl_intg_err	7.490s	4.275ms	5	5	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	7.490s	4.275ms	5	5	100.00
V2S		TOTAL			8	8	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	18.030s	7.624ms	15	15	100.00
V3		TOTAL			15	15	100.00
		TOTAL			239	241	99.17

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	14	87.50
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.45	99.05	96.03	100.00	100.00	98.64	95.95	92.46

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:

  • Test adc_ctrl_clock_gating has 1 failures.

    • 7.adc_ctrl_clock_gating.7331562762922401190917368725237788729377203539047886105675642546415492697055
      Line 345, in log /home/runner/_work/pavona/pavona/scratch/main/adc_ctrl-sim-vcs/7.adc_ctrl_clock_gating/latest/run.log

        UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test adc_ctrl_stress_all has 1 failures.

    • 18.adc_ctrl_stress_all.38415432037149301420945727594900540947456626108865610378539435617916725393155
      Line 374, in log /home/runner/_work/pavona/pavona/scratch/main/adc_ctrl-sim-vcs/18.adc_ctrl_stress_all/latest/run.log

        UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---