AES/MASKED Simulation Results

Saturday June 06 2026 03:15:30 UTC

GitHub Revision: `285e653a0b`

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	1.380s	192.695us	1	1	100.00
V1	smoke	aes_smoke	1.710s	68.876us	1	1	100.00
V1	csr_hw_reset	aes_csr_hw_reset	0.910s	77.887us	5	5	100.00
V1	csr_rw	aes_csr_rw	0.960s	63.198us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	5.030s	4.130ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	2.060s	119.152us	4	5	80.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	1.230s	85.166us	4	4	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	0.960s	63.198us	20	20	100.00
		aes_csr_aliasing	2.060s	119.152us	4	5	80.00
V1		TOTAL			40	41	97.56
V2	algorithm	aes_smoke	1.710s	68.876us	1	1	100.00
		aes_config_error	2.040s	98.678us	14	14	100.00
		aes_stress	3.390s	325.460us	4	4	100.00
V2	key_length	aes_smoke	1.710s	68.876us	1	1	100.00
		aes_config_error	2.040s	98.678us	14	14	100.00
		aes_stress	3.390s	325.460us	4	4	100.00
V2	back2back	aes_stress	3.390s	325.460us	4	4	100.00
		aes_b2b	10.010s	257.796us	1	1	100.00
V2	backpressure	aes_stress	3.390s	325.460us	4	4	100.00
V2	multi_message	aes_smoke	1.710s	68.876us	1	1	100.00
		aes_config_error	2.040s	98.678us	14	14	100.00
		aes_stress	3.390s	325.460us	4	4	100.00
		aes_alert_reset	12.410s	1.338ms	9	9	100.00
V2	failure_test	aes_man_cfg_err	1.060s	109.124us	1	1	100.00
		aes_config_error	2.040s	98.678us	14	14	100.00
		aes_alert_reset	12.410s	1.338ms	9	9	100.00
V2	trigger_clear_test	aes_clear	9.440s	583.604us	5	5	100.00
V2	nist_test_vectors	aes_nist_vectors	19.110s	2.078ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	12.410s	1.338ms	9	9	100.00
V2	stress	aes_stress	3.390s	325.460us	4	4	100.00
V2	sideload	aes_stress	3.390s	325.460us	4	4	100.00
		aes_sideload	2.810s	97.576us	6	6	100.00
V2	deinitialization	aes_deinit	2.590s	401.076us	3	3	100.00
V2	stress_all	aes_stress_all	44.330s	1.431ms	7	7	100.00
V2	alert_test	aes_alert_test	0.950s	347.037us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	2.190s	118.778us	5	5	100.00
V2	tl_d_illegal_access	aes_tl_errors	2.190s	118.778us	5	5	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	0.910s	77.887us	5	5	100.00
		aes_csr_rw	0.960s	63.198us	20	20	100.00
		aes_csr_aliasing	2.060s	119.152us	4	5	80.00
		aes_same_csr_outstanding	1.240s	112.174us	3	3	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	0.910s	77.887us	5	5	100.00
		aes_csr_rw	0.960s	63.198us	20	20	100.00
		aes_csr_aliasing	2.060s	119.152us	4	5	80.00
		aes_same_csr_outstanding	1.240s	112.174us	3	3	100.00
V2		TOTAL			109	109	100.00
V2S	reseeding	aes_reseed	3.050s	191.418us	3	3	100.00
V2S	fault_inject	aes_fi	1.910s	318.495us	1	1	100.00
		aes_control_fi	15.930s	10.030ms	312	322	96.89
		aes_cipher_fi	17.530s	10.014ms	379	383	98.96
V2S	shadow_reg_update_error	aes_shadow_reg_errors	1.000s	139.489us	3	3	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	1.000s	139.489us	3	3	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	1.000s	139.489us	3	3	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	1.000s	139.489us	3	3	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	1.800s	145.983us	4	4	100.00
V2S	tl_intg_err	aes_sec_cm	4.750s	1.583ms	3	3	100.00
		aes_tl_intg_err	2.290s	973.482us	10	10	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	2.290s	973.482us	10	10	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	12.410s	1.338ms	9	9	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	1.000s	139.489us	3	3	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	1.710s	68.876us	1	1	100.00
		aes_stress	3.390s	325.460us	4	4	100.00
		aes_alert_reset	12.410s	1.338ms	9	9	100.00
		aes_core_fi	12.990s	10.038ms	46	47	97.87
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	1.000s	139.489us	3	3	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	1.010s	94.673us	1	1	100.00
		aes_stress	3.390s	325.460us	4	4	100.00
V2S	sec_cm_key_sideload	aes_stress	3.390s	325.460us	4	4	100.00
		aes_sideload	2.810s	97.576us	6	6	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	1.010s	94.673us	1	1	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	1.010s	94.673us	1	1	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	1.010s	94.673us	1	1	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	1.010s	94.673us	1	1	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	1.010s	94.673us	1	1	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	3.390s	325.460us	4	4	100.00
V2S	sec_cm_key_masking	aes_stress	3.390s	325.460us	4	4	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	1.910s	318.495us	1	1	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	1.910s	318.495us	1	1	100.00
		aes_control_fi	15.930s	10.030ms	312	322	96.89
		aes_cipher_fi	17.530s	10.014ms	379	383	98.96
		aes_ctr_fi	3.080s	1.255ms	24	24	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	1.910s	318.495us	1	1	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	1.910s	318.495us	1	1	100.00
		aes_control_fi	15.930s	10.030ms	312	322	96.89
		aes_cipher_fi	17.530s	10.014ms	379	383	98.96
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	17.530s	10.014ms	379	383	98.96
V2S	sec_cm_ctr_fsm_sparse	aes_fi	1.910s	318.495us	1	1	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	1.910s	318.495us	1	1	100.00
		aes_control_fi	15.930s	10.030ms	312	322	96.89
		aes_ctr_fi	3.080s	1.255ms	24	24	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	1.910s	318.495us	1	1	100.00
		aes_control_fi	15.930s	10.030ms	312	322	96.89
		aes_cipher_fi	17.530s	10.014ms	379	383	98.96
		aes_ctr_fi	3.080s	1.255ms	24	24	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	12.410s	1.338ms	9	9	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	1.910s	318.495us	1	1	100.00
		aes_control_fi	15.930s	10.030ms	312	322	96.89
		aes_cipher_fi	17.530s	10.014ms	379	383	98.96
		aes_ctr_fi	3.080s	1.255ms	24	24	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	1.910s	318.495us	1	1	100.00
		aes_control_fi	15.930s	10.030ms	312	322	96.89
		aes_cipher_fi	17.530s	10.014ms	379	383	98.96
		aes_ctr_fi	3.080s	1.255ms	24	24	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	1.910s	318.495us	1	1	100.00
		aes_control_fi	15.930s	10.030ms	312	322	96.89
		aes_ctr_fi	3.080s	1.255ms	24	24	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	1.910s	318.495us	1	1	100.00
		aes_control_fi	15.930s	10.030ms	312	322	96.89
		aes_cipher_fi	17.530s	10.014ms	379	383	98.96
V2S		TOTAL			786	801	98.13
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	35.410s	3.200ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			935	961	97.29

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	6	85.71
V2	13	13	13	100.00
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.73	99.63	97.45	100.00	100.00	99.68	98.38	74.94

Failure Buckets

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.33509180028898315696349628117274730790620585426796982557118916586525220657477
Line 341, in log /home/runner/_work/pavona/pavona/scratch/main/aes_masked-sim-vcs/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 381336331 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 381336331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.80376756730224218484375503155005235261839942962611256300070814192559833724125
Line 459, in log /home/runner/_work/pavona/pavona/scratch/main/aes_masked-sim-vcs/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1968196482 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1968196482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Job timed out after * minutes has 5 failures:
- Test aes_control_fi has 5 failures.
  - 254.aes_control_fi.63067246314935684147127697309508213564930784740883374755030559279667004312671
    Log /home/runner/_work/pavona/pavona/scratch/main/aes_masked-sim-vcs/254.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 267.aes_control_fi.50687527494745729307339243328929767683715602927891372400291437082306062679587
    Log /home/runner/_work/pavona/pavona/scratch/main/aes_masked-sim-vcs/267.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 3 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_control_fi has 5 failures.
  - 274.aes_control_fi.33217391303014684977394739257851516355596998099438584968595447596590888932680
    Line 131, in log /home/runner/_work/pavona/pavona/scratch/main/aes_masked-sim-vcs/274.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10005645209 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005645209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 275.aes_control_fi.77643773948416059011809575864435429607918421536892425066280763479388559486167
    Line 147, in log /home/runner/_work/pavona/pavona/scratch/main/aes_masked-sim-vcs/275.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10017627119 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10017627119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_cipher_fi has 4 failures.
  - 269.aes_cipher_fi.22502145185401403048431856153625448153694964903462752259127643812790232936675
    Line 132, in log /home/runner/_work/pavona/pavona/scratch/main/aes_masked-sim-vcs/269.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10008285998 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008285998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 301.aes_cipher_fi.68630275602599700238433947967425548592503085509225829588693738502243289240295
    Line 141, in log /home/runner/_work/pavona/pavona/scratch/main/aes_masked-sim-vcs/301.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10013967076 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013967076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 1.aes_stress_all_with_rand_reset.49991373937112617013224782469050746109493346949795194157007800212494889143042
    Line 819, in log /home/runner/_work/pavona/pavona/scratch/main/aes_masked-sim-vcs/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1043583017 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 1043583017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.aes_stress_all_with_rand_reset.79919520966380543008453871779040181112240767226806120131948969182050752748315
    Line 813, in log /home/runner/_work/pavona/pavona/scratch/main/aes_masked-sim-vcs/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 9664934895 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 9664934895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '((((state_q[*] != $past(state_q[*], gen_sec_cm_key_masking_svas.NumCyclesPerRound)) || ($past(state_q[*], gen_sec_cm_key_masking_svas.NumCyclesPerRound) != $past(state_q[*], (* * gen_sec_cm_key_masking_svas.NumCyclesPerRound)))) || (SecAllowForcingMasks && force_masks_i)) || (dec_key_gen_o == SP2V_HIGH))' has 1 failures:
- Test aes_csr_aliasing has 1 failures.
  - 4.aes_csr_aliasing.105313133127695754312775570612113087851928458064505940901617942075706967858379
    Line 101, in log /home/runner/_work/pavona/pavona/scratch/main/aes_masked-sim-vcs/4.aes_csr_aliasing/latest/run.log
```
      Offending '((((state_q[1] != $past(state_q[1], gen_sec_cm_key_masking_svas.NumCyclesPerRound)) || ($past(state_q[1], gen_sec_cm_key_masking_svas.NumCyclesPerRound) != $past(state_q[1], (2 * gen_sec_cm_key_masking_svas.NumCyclesPerRound)))) || (SecAllowForcingMasks && force_masks_i)) || (dec_key_gen_o == SP2V_HIGH))'
  UVM_ERROR @  54402749 ps: (aes_cipher_core.sv:872) [ASSERT FAILED] AesSecCmKeyMaskingStateShare
  UVM_INFO @  54402749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:1237) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 7.aes_stress_all_with_rand_reset.73639861601874019956735784905778546197438720365745752407143048127352081989040
    Line 172, in log /home/runner/_work/pavona/pavona/scratch/main/aes_masked-sim-vcs/7.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 952326476 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 952326476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 35.aes_core_fi.85688261056223484172729588461455745012008750051805568741660831886522666402950
    Line 139, in log /home/runner/_work/pavona/pavona/scratch/main/aes_masked-sim-vcs/35.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10037863330 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10037863330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```