AES/UNMASKED Simulation Results

Saturday June 06 2026 03:15:30 UTC

GitHub Revision: 285e653a0b

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	0.940s	65.930us	1	1	100.00
V1	smoke	aes_smoke	1.120s	59.382us	1	1	100.00
V1	csr_hw_reset	aes_csr_hw_reset	0.710s	76.732us	5	5	100.00
V1	csr_rw	aes_csr_rw	0.790s	58.220us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	5.260s	2.975ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	1.970s	921.031us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	0.960s	70.136us	3	3	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	0.790s	58.220us	20	20	100.00
		aes_csr_aliasing	1.970s	921.031us	5	5	100.00
V1		TOTAL			40	40	100.00
V2	algorithm	aes_smoke	1.120s	59.382us	1	1	100.00
		aes_config_error	1.860s	312.119us	13	13	100.00
		aes_stress	1.580s	82.879us	5	5	100.00
V2	key_length	aes_smoke	1.120s	59.382us	1	1	100.00
		aes_config_error	1.860s	312.119us	13	13	100.00
		aes_stress	1.580s	82.879us	5	5	100.00
V2	back2back	aes_stress	1.580s	82.879us	5	5	100.00
		aes_b2b	3.350s	109.550us	3	3	100.00
V2	backpressure	aes_stress	1.580s	82.879us	5	5	100.00
V2	multi_message	aes_smoke	1.120s	59.382us	1	1	100.00
		aes_config_error	1.860s	312.119us	13	13	100.00
		aes_stress	1.580s	82.879us	5	5	100.00
		aes_alert_reset	1.990s	249.125us	9	9	100.00
V2	failure_test	aes_man_cfg_err	0.860s	66.158us	1	1	100.00
		aes_config_error	1.860s	312.119us	13	13	100.00
		aes_alert_reset	1.990s	249.125us	9	9	100.00
V2	trigger_clear_test	aes_clear	2.010s	76.419us	4	4	100.00
V2	nist_test_vectors	aes_nist_vectors	2.730s	314.667us	1	1	100.00
V2	reset_recovery	aes_alert_reset	1.990s	249.125us	9	9	100.00
V2	stress	aes_stress	1.580s	82.879us	5	5	100.00
V2	sideload	aes_stress	1.580s	82.879us	5	5	100.00
		aes_sideload	1.630s	115.211us	5	5	100.00
V2	deinitialization	aes_deinit	2.080s	197.482us	1	1	100.00
V2	stress_all	aes_stress_all	10.260s	1.347ms	6	6	100.00
V2	alert_test	aes_alert_test	0.800s	66.333us	3	3	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	2.110s	744.981us	4	4	100.00
V2	tl_d_illegal_access	aes_tl_errors	2.110s	744.981us	4	4	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	0.710s	76.732us	5	5	100.00
		aes_csr_rw	0.790s	58.220us	20	20	100.00
		aes_csr_aliasing	1.970s	921.031us	5	5	100.00
		aes_same_csr_outstanding	0.900s	83.497us	3	3	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	0.710s	76.732us	5	5	100.00
		aes_csr_rw	0.790s	58.220us	20	20	100.00
		aes_csr_aliasing	1.970s	921.031us	5	5	100.00
		aes_same_csr_outstanding	0.900s	83.497us	3	3	100.00
V2		TOTAL			58	58	100.00
V2S	reseeding	aes_reseed	1.780s	141.239us	3	3	100.00
V2S	fault_inject	aes_fi	1.540s	73.097us	4	4	100.00
		aes_control_fi	15.570s	10.003ms	325	334	97.31
		aes_cipher_fi	8.970s	10.004ms	236	244	96.72
V2S	shadow_reg_update_error	aes_shadow_reg_errors	1.000s	149.087us	4	4	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	1.000s	149.087us	4	4	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	1.000s	149.087us	4	4	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	1.000s	149.087us	4	4	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	1.650s	426.504us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	2.240s	573.877us	3	3	100.00
		aes_tl_intg_err	2.130s	491.908us	11	11	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	2.130s	491.908us	11	11	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	1.990s	249.125us	9	9	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	1.000s	149.087us	4	4	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	1.120s	59.382us	1	1	100.00
		aes_stress	1.580s	82.879us	5	5	100.00
		aes_alert_reset	1.990s	249.125us	9	9	100.00
		aes_core_fi	11.300s	10.009ms	40	41	97.56
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	1.000s	149.087us	4	4	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	1.060s	76.241us	3	3	100.00
		aes_stress	1.580s	82.879us	5	5	100.00
V2S	sec_cm_key_sideload	aes_stress	1.580s	82.879us	5	5	100.00
		aes_sideload	1.630s	115.211us	5	5	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	1.060s	76.241us	3	3	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	1.060s	76.241us	3	3	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	1.060s	76.241us	3	3	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	1.060s	76.241us	3	3	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	1.060s	76.241us	3	3	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	1.580s	82.879us	5	5	100.00
V2S	sec_cm_key_masking	aes_stress	1.580s	82.879us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	1.540s	73.097us	4	4	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	1.540s	73.097us	4	4	100.00
		aes_control_fi	15.570s	10.003ms	325	334	97.31
		aes_cipher_fi	8.970s	10.004ms	236	244	96.72
		aes_ctr_fi	1.090s	55.092us	23	23	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	1.540s	73.097us	4	4	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	1.540s	73.097us	4	4	100.00
		aes_control_fi	15.570s	10.003ms	325	334	97.31
		aes_cipher_fi	8.970s	10.004ms	236	244	96.72
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	8.970s	10.004ms	236	244	96.72
V2S	sec_cm_ctr_fsm_sparse	aes_fi	1.540s	73.097us	4	4	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	1.540s	73.097us	4	4	100.00
		aes_control_fi	15.570s	10.003ms	325	334	97.31
		aes_ctr_fi	1.090s	55.092us	23	23	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	1.540s	73.097us	4	4	100.00
		aes_control_fi	15.570s	10.003ms	325	334	97.31
		aes_cipher_fi	8.970s	10.004ms	236	244	96.72
		aes_ctr_fi	1.090s	55.092us	23	23	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	1.990s	249.125us	9	9	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	1.540s	73.097us	4	4	100.00
		aes_control_fi	15.570s	10.003ms	325	334	97.31
		aes_cipher_fi	8.970s	10.004ms	236	244	96.72
		aes_ctr_fi	1.090s	55.092us	23	23	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	1.540s	73.097us	4	4	100.00
		aes_control_fi	15.570s	10.003ms	325	334	97.31
		aes_cipher_fi	8.970s	10.004ms	236	244	96.72
		aes_ctr_fi	1.090s	55.092us	23	23	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	1.540s	73.097us	4	4	100.00
		aes_control_fi	15.570s	10.003ms	325	334	97.31
		aes_ctr_fi	1.090s	55.092us	23	23	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	1.540s	73.097us	4	4	100.00
		aes_control_fi	15.570s	10.003ms	325	334	97.31
		aes_cipher_fi	8.970s	10.004ms	236	244	96.72
V2S		TOTAL			672	690	97.39
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	11.490s	476.955us	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			770	798	96.49

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.63	97.44	96.25	99.73	92.68	98.35	97.92	66.05

Failure Buckets

• UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 8 failures:

  • Test aes_stress_all_with_rand_reset has 8 failures.

    • 0.aes_stress_all_with_rand_reset.95751697158174568435509686933243884929127508267250713984347100240301727690979
      Line 609, in log /home/runner/_work/pavona/pavona/scratch/main/aes_unmasked-sim-vcs/0.aes_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 361135292 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
        UVM_INFO @ 361135292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.aes_stress_all_with_rand_reset.39314769385117542397598001232073442589105892229243799098276344465240776411206
      Line 201, in log /home/runner/_work/pavona/pavona/scratch/main/aes_unmasked-sim-vcs/1.aes_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  92921882 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
        UVM_INFO @  92921882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 6 more failures.

• Job timed out after * minutes has 7 failures:

  • Test aes_cipher_fi has 4 failures.

    • 175.aes_cipher_fi.79912440069101456355681504056292896876735233909249041582422885168077472237411
      Log /home/runner/_work/pavona/pavona/scratch/main/aes_unmasked-sim-vcs/175.aes_cipher_fi/latest/run.log

        Job timed out after 1 minutes
      

    • 179.aes_cipher_fi.73996444496950633800680319911892969820446381010577209562137109895677437861892
      Log /home/runner/_work/pavona/pavona/scratch/main/aes_unmasked-sim-vcs/179.aes_cipher_fi/latest/run.log

        Job timed out after 1 minutes
      

    • ... and 2 more failures.

  • Test aes_control_fi has 3 failures.

    • 245.aes_control_fi.35381099462723399812784390270386899448104507531060351010617329035473264977700
      Log /home/runner/_work/pavona/pavona/scratch/main/aes_unmasked-sim-vcs/245.aes_control_fi/latest/run.log

        Job timed out after 1 minutes
      

    • 260.aes_control_fi.54540125801568704368802312290545489867905066318594353656129726850997087185151
      Log /home/runner/_work/pavona/pavona/scratch/main/aes_unmasked-sim-vcs/260.aes_control_fi/latest/run.log

        Job timed out after 1 minutes
      

    • ... and 1 more failures.

• UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 6 failures:

  • Test aes_control_fi has 6 failures.

    • 238.aes_control_fi.81310512299411431495968990111172611422960158576575609462937248061666218854159
      Line 145, in log /home/runner/_work/pavona/pavona/scratch/main/aes_unmasked-sim-vcs/238.aes_control_fi/latest/run.log

        UVM_FATAL @ 10006470270 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
        UVM_INFO @ 10006470270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 254.aes_control_fi.21005568870007138098614701003385784378470982545446950090572297551679521554726
      Line 137, in log /home/runner/_work/pavona/pavona/scratch/main/aes_unmasked-sim-vcs/254.aes_control_fi/latest/run.log

        UVM_FATAL @ 10002977744 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
        UVM_INFO @ 10002977744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 4 more failures.

• UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 4 failures:

  • Test aes_cipher_fi has 4 failures.

    • 188.aes_cipher_fi.47759669132713382874625474503899506671591754362783815845947224525339080598627
      Line 136, in log /home/runner/_work/pavona/pavona/scratch/main/aes_unmasked-sim-vcs/188.aes_cipher_fi/latest/run.log

        UVM_FATAL @ 10003883003 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
        UVM_INFO @ 10003883003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 213.aes_cipher_fi.3043479903594215682736805216924941472918956079634309238918471977681971940988
      Line 136, in log /home/runner/_work/pavona/pavona/scratch/main/aes_unmasked-sim-vcs/213.aes_cipher_fi/latest/run.log

        UVM_FATAL @ 10007814536 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
        UVM_INFO @ 10007814536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 2 more failures.

• UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 2 failures:

  • Test aes_stress_all_with_rand_reset has 2 failures.

    • 4.aes_stress_all_with_rand_reset.76412788786187141161487168331448643984445999377823917934959242982213196041197
      Line 145, in log /home/runner/_work/pavona/pavona/scratch/main/aes_unmasked-sim-vcs/4.aes_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @  30611279 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
        UVM_INFO @  30611279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 7.aes_stress_all_with_rand_reset.83769536523355417534824500025613759015641944230851211572761902838281209924505
      Line 204, in log /home/runner/_work/pavona/pavona/scratch/main/aes_unmasked-sim-vcs/7.aes_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 428605681 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
        UVM_INFO @ 428605681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:

  • Test aes_core_fi has 1 failures.

    • 27.aes_core_fi.112470492872012699625087136553273279886228048357947028546343172829738481899188
      Line 134, in log /home/runner/_work/pavona/pavona/scratch/main/aes_unmasked-sim-vcs/27.aes_core_fi/latest/run.log

        UVM_FATAL @ 10008579297 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
        UVM_INFO @ 10008579297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---