ALERT_HANDLER/DRAGONFLY Simulation Results

Saturday June 06 2026 03:15:30 UTC

GitHub Revision: 285e653a0b

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.288m	6.014ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	8.250s	217.445us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	8.770s	1.103ms	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	6.405m	46.192ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	3.865m	4.927ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	12.740s	276.990us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	8.770s	1.103ms	20	20	100.00
		alert_handler_csr_aliasing	3.865m	4.927ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	4.335m	40.243ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.100m	4.587ms	50	50	100.00
V2	entropy	alert_handler_entropy	36.757m	191.281ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.172m	2.623ms	48	50	96.00
V2	clk_skew	alert_handler_smoke	1.288m	6.014ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.408m	4.985ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.326m	7.102ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	6.482m	51.256ms	7	50	14.00
V2	lpg	alert_handler_lpg	47.470m	65.703ms	50	50	100.00
		alert_handler_lpg_stub_clk	42.393m	159.962ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.016h	269.986ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	1.056m	8.745ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.680s	54.041us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.950s	16.750us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	22.580s	1.910ms	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	22.580s	1.910ms	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	8.250s	217.445us	5	5	100.00
		alert_handler_csr_rw	8.770s	1.103ms	20	20	100.00
		alert_handler_csr_aliasing	3.865m	4.927ms	5	5	100.00
		alert_handler_same_csr_outstanding	52.010s	1.451ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	8.250s	217.445us	5	5	100.00
		alert_handler_csr_rw	8.770s	1.103ms	20	20	100.00
		alert_handler_csr_aliasing	3.865m	4.927ms	5	5	100.00
		alert_handler_same_csr_outstanding	52.010s	1.451ms	20	20	100.00
V2		TOTAL			585	630	92.86
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	5.736m	6.347ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	5.736m	6.347ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	5.736m	6.347ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	5.736m	6.347ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	15.466m	60.530ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	27.670s	852.463us	5	5	100.00
		alert_handler_tl_intg_err	54.650s	1.294ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	54.650s	1.294ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	5.736m	6.347ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.288m	6.014ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.288m	6.014ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.288m	6.014ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.288m	6.014ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.172m	2.623ms	48	50	96.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	47.470m	65.703ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.172m	2.623ms	48	50	96.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	36.757m	191.281ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	36.757m	191.281ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	27.670s	852.463us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	27.670s	852.463us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	27.670s	852.463us	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	27.670s	852.463us	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	27.670s	852.463us	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	27.670s	852.463us	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	27.670s	852.463us	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	27.670s	852.463us	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	27.670s	852.463us	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	8.057m	20.128ms	31	50	62.00
V3		TOTAL			31	50	62.00
		TOTAL			786	850	92.47

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	13	86.67
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.03	99.99	98.60	97.34	100.00	99.99	98.92	98.38

Failure Buckets

• UVM_ERROR (alert_handler_scoreboard.sv:483) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state has 37 failures:

  • Test alert_handler_ping_timeout has 37 failures.

    • 1.alert_handler_ping_timeout.45747979922962223853809002015260400302268336863787106923869485486618125960522
      Line 91, in log /home/runner/_work/pavona/pavona/scratch/main/alert_handler_top_dragonfly-sim-vcs/1.alert_handler_ping_timeout/latest/run.log

        UVM_ERROR @ 6210267610 ps: (alert_handler_scoreboard.sv:483) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state
        UVM_INFO @ 6210267610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.alert_handler_ping_timeout.7014818184954267308696159741352712014583760366321007644879995888492238058510
      Line 103, in log /home/runner/_work/pavona/pavona/scratch/main/alert_handler_top_dragonfly-sim-vcs/2.alert_handler_ping_timeout/latest/run.log

        UVM_ERROR @ 14979984158 ps: (alert_handler_scoreboard.sv:483) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state
        UVM_INFO @ 14979984158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 35 more failures.

• UVM_ERROR (cip_base_vseq.sv:1237) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 18 failures:

  • Test alert_handler_stress_all_with_rand_reset has 18 failures.

    • 3.alert_handler_stress_all_with_rand_reset.70586417878458184615674024646879679141872906305913925595979058032552394012617
      Line 127, in log /home/runner/_work/pavona/pavona/scratch/main/alert_handler_top_dragonfly-sim-vcs/3.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2283460032 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2283460032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.alert_handler_stress_all_with_rand_reset.68789921910661877011635103198246671234009111494172388853251468353090489474985
      Line 106, in log /home/runner/_work/pavona/pavona/scratch/main/alert_handler_top_dragonfly-sim-vcs/4.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 558396856 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 558396856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 16 more failures.

• UVM_ERROR (alert_handler_scoreboard.sv:595) [scoreboard] Check failed crashdump_val.loc_alert_cause[i] ==gmv(ral.loc_alert_cause[i]) (* [] vs * [])` has 6 failures:

  • Test alert_handler_ping_timeout has 6 failures.

    • 5.alert_handler_ping_timeout.15839909781248596433412360416737078913935447768145711920630993360009301231262
      Line 87, in log /home/runner/_work/pavona/pavona/scratch/main/alert_handler_top_dragonfly-sim-vcs/5.alert_handler_ping_timeout/latest/run.log

        UVM_ERROR @ 137383885 ps: (alert_handler_scoreboard.sv:595) [uvm_test_top.env.scoreboard] Check failed crashdump_val.loc_alert_cause[i] == `gmv(ral.loc_alert_cause[i]) (1 [0x1] vs 0 [0x0])
        UVM_INFO @ 137383885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 12.alert_handler_ping_timeout.48776976704007051701917126682326017341269571791130451365111869185520459173835
      Line 87, in log /home/runner/_work/pavona/pavona/scratch/main/alert_handler_top_dragonfly-sim-vcs/12.alert_handler_ping_timeout/latest/run.log

        UVM_ERROR @ 503708594 ps: (alert_handler_scoreboard.sv:595) [uvm_test_top.env.scoreboard] Check failed crashdump_val.loc_alert_cause[i] == `gmv(ral.loc_alert_cause[i]) (1 [0x1] vs 0 [0x0])
        UVM_INFO @ 503708594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 4 more failures.

• UVM_ERROR (alert_handler_scoreboard.sv:487) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classc_esc_cnt has 1 failures:

  • Test alert_handler_sig_int_fail has 1 failures.

    • 8.alert_handler_sig_int_fail.30376407711619055276714007877974932765381039436932166295254006665138948275826
      Line 93, in log /home/runner/_work/pavona/pavona/scratch/main/alert_handler_top_dragonfly-sim-vcs/8.alert_handler_sig_int_fail/latest/run.log

        UVM_ERROR @ 265513066 ps: (alert_handler_scoreboard.sv:487) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (117 [0x75] vs 124 [0x7c]) reg name: alert_handler_reg_block.classc_esc_cnt
        UVM_INFO @ 265513066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1150) [alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 36.alert_handler_stress_all_with_rand_reset.24851814442601525625281156220022066466175755270792406257687804231918434011160
      Line 120, in log /home/runner/_work/pavona/pavona/scratch/main/alert_handler_top_dragonfly-sim-vcs/36.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 483694627 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 483694627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (alert_handler_scoreboard.sv:487) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classc_state has 1 failures:

  • Test alert_handler_sig_int_fail has 1 failures.

    • 37.alert_handler_sig_int_fail.11515844886531305008932793559351905611201213505216396549918053803827738086120
      Line 95, in log /home/runner/_work/pavona/pavona/scratch/main/alert_handler_top_dragonfly-sim-vcs/37.alert_handler_sig_int_fail/latest/run.log

        UVM_ERROR @ 685921185 ps: (alert_handler_scoreboard.sv:487) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (7 [0x7] vs 6 [0x6]) reg name: alert_handler_reg_block.classc_state
        UVM_INFO @ 685921185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---