285e653a0b| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | alert_handler_smoke | 49.540s | 1.797ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | alert_handler_csr_hw_reset | 8.570s | 139.222us | 5 | 5 | 100.00 |
| V1 | csr_rw | alert_handler_csr_rw | 6.740s | 351.048us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | alert_handler_csr_bit_bash | 3.601m | 12.152ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | alert_handler_csr_aliasing | 2.964m | 17.543ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | alert_handler_csr_mem_rw_with_rand_reset | 11.550s | 2.124ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | alert_handler_csr_rw | 6.740s | 351.048us | 20 | 20 | 100.00 |
| alert_handler_csr_aliasing | 2.964m | 17.543ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | esc_accum | alert_handler_esc_alert_accum | 3.802m | 10.781ms | 50 | 50 | 100.00 |
| V2 | esc_timeout | alert_handler_esc_intr_timeout | 58.550s | 1.209ms | 50 | 50 | 100.00 |
| V2 | entropy | alert_handler_entropy | 35.152m | 87.372ms | 48 | 50 | 96.00 |
| V2 | sig_int_fail | alert_handler_sig_int_fail | 37.710s | 735.331us | 49 | 50 | 98.00 |
| V2 | clk_skew | alert_handler_smoke | 49.540s | 1.797ms | 50 | 50 | 100.00 |
| V2 | random_alerts | alert_handler_random_alerts | 1.054m | 5.450ms | 50 | 50 | 100.00 |
| V2 | random_classes | alert_handler_random_classes | 51.690s | 1.069ms | 50 | 50 | 100.00 |
| V2 | ping_timeout | alert_handler_ping_timeout | 5.455m | 27.641ms | 20 | 50 | 40.00 |
| V2 | lpg | alert_handler_lpg | 34.892m | 120.335ms | 45 | 50 | 90.00 |
| alert_handler_lpg_stub_clk | 36.013m | 208.816ms | 49 | 50 | 98.00 | ||
| V2 | stress_all | alert_handler_stress_all | 32.187m | 119.760ms | 49 | 50 | 98.00 |
| V2 | alert_handler_entropy_stress_test | alert_handler_entropy_stress | 43.360s | 1.301ms | 20 | 20 | 100.00 |
| V2 | alert_handler_alert_accum_saturation | alert_handler_alert_accum_saturation | 4.120s | 54.434us | 20 | 20 | 100.00 |
| V2 | intr_test | alert_handler_intr_test | 1.730s | 11.902us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | alert_handler_tl_errors | 19.350s | 297.669us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | alert_handler_tl_errors | 19.350s | 297.669us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | alert_handler_csr_hw_reset | 8.570s | 139.222us | 5 | 5 | 100.00 |
| alert_handler_csr_rw | 6.740s | 351.048us | 20 | 20 | 100.00 | ||
| alert_handler_csr_aliasing | 2.964m | 17.543ms | 5 | 5 | 100.00 | ||
| alert_handler_same_csr_outstanding | 35.890s | 670.916us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | alert_handler_csr_hw_reset | 8.570s | 139.222us | 5 | 5 | 100.00 |
| alert_handler_csr_rw | 6.740s | 351.048us | 20 | 20 | 100.00 | ||
| alert_handler_csr_aliasing | 2.964m | 17.543ms | 5 | 5 | 100.00 | ||
| alert_handler_same_csr_outstanding | 35.890s | 670.916us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 590 | 630 | 93.65 | |||
| V2S | shadow_reg_update_error | alert_handler_shadow_reg_errors | 3.951m | 6.821ms | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | alert_handler_shadow_reg_errors | 3.951m | 6.821ms | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | alert_handler_shadow_reg_errors | 3.951m | 6.821ms | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | alert_handler_shadow_reg_errors | 3.951m | 6.821ms | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | alert_handler_shadow_reg_errors_with_csr_rw | 11.585m | 104.235ms | 20 | 20 | 100.00 |
| V2S | tl_intg_err | alert_handler_sec_cm | 25.590s | 731.420us | 5 | 5 | 100.00 |
| alert_handler_tl_intg_err | 1.022m | 1.233ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | alert_handler_tl_intg_err | 1.022m | 1.233ms | 20 | 20 | 100.00 |
| V2S | sec_cm_config_shadow | alert_handler_shadow_reg_errors | 3.951m | 6.821ms | 20 | 20 | 100.00 |
| V2S | sec_cm_ping_timer_config_regwen | alert_handler_smoke | 49.540s | 1.797ms | 50 | 50 | 100.00 |
| V2S | sec_cm_alert_config_regwen | alert_handler_smoke | 49.540s | 1.797ms | 50 | 50 | 100.00 |
| V2S | sec_cm_alert_loc_config_regwen | alert_handler_smoke | 49.540s | 1.797ms | 50 | 50 | 100.00 |
| V2S | sec_cm_class_config_regwen | alert_handler_smoke | 49.540s | 1.797ms | 50 | 50 | 100.00 |
| V2S | sec_cm_alert_intersig_diff | alert_handler_sig_int_fail | 37.710s | 735.331us | 49 | 50 | 98.00 |
| V2S | sec_cm_lpg_intersig_mubi | alert_handler_lpg | 34.892m | 120.335ms | 45 | 50 | 90.00 |
| V2S | sec_cm_esc_intersig_diff | alert_handler_sig_int_fail | 37.710s | 735.331us | 49 | 50 | 98.00 |
| V2S | sec_cm_alert_rx_intersig_bkgn_chk | alert_handler_entropy | 35.152m | 87.372ms | 48 | 50 | 96.00 |
| V2S | sec_cm_esc_tx_intersig_bkgn_chk | alert_handler_entropy | 35.152m | 87.372ms | 48 | 50 | 96.00 |
| V2S | sec_cm_esc_timer_fsm_sparse | alert_handler_sec_cm | 25.590s | 731.420us | 5 | 5 | 100.00 |
| V2S | sec_cm_ping_timer_fsm_sparse | alert_handler_sec_cm | 25.590s | 731.420us | 5 | 5 | 100.00 |
| V2S | sec_cm_esc_timer_fsm_local_esc | alert_handler_sec_cm | 25.590s | 731.420us | 5 | 5 | 100.00 |
| V2S | sec_cm_ping_timer_fsm_local_esc | alert_handler_sec_cm | 25.590s | 731.420us | 5 | 5 | 100.00 |
| V2S | sec_cm_esc_timer_fsm_global_esc | alert_handler_sec_cm | 25.590s | 731.420us | 5 | 5 | 100.00 |
| V2S | sec_cm_accu_ctr_redun | alert_handler_sec_cm | 25.590s | 731.420us | 5 | 5 | 100.00 |
| V2S | sec_cm_esc_timer_ctr_redun | alert_handler_sec_cm | 25.590s | 731.420us | 5 | 5 | 100.00 |
| V2S | sec_cm_ping_timer_ctr_redun | alert_handler_sec_cm | 25.590s | 731.420us | 5 | 5 | 100.00 |
| V2S | sec_cm_ping_timer_lfsr_redun | alert_handler_sec_cm | 25.590s | 731.420us | 5 | 5 | 100.00 |
| V2S | TOTAL | 65 | 65 | 100.00 | |||
| V3 | stress_all_with_rand_reset | alert_handler_stress_all_with_rand_reset | 5.583m | 28.443ms | 38 | 50 | 76.00 |
| V3 | TOTAL | 38 | 50 | 76.00 | |||
| TOTAL | 798 | 850 | 93.88 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 15 | 15 | 9 | 60.00 |
| V2S | 4 | 4 | 4 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.15 | 99.99 | 98.70 | 97.09 | 100.00 | 99.99 | 98.88 | 99.40 |
UVM_ERROR (alert_handler_scoreboard.sv:483) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state has 25 failures:
0.alert_handler_ping_timeout.92789516789724679505371983347392882166009885608897773984119295320781357563700
Line 106, in log /home/runner/_work/pavona/pavona/scratch/main/alert_handler_top_egret-sim-vcs/0.alert_handler_ping_timeout/latest/run.log
UVM_ERROR @ 4909261886 ps: (alert_handler_scoreboard.sv:483) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state
UVM_INFO @ 4909261886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.alert_handler_ping_timeout.20749941119800352426441010823677432545504089289016242291707594284104728932704
Line 112, in log /home/runner/_work/pavona/pavona/scratch/main/alert_handler_top_egret-sim-vcs/1.alert_handler_ping_timeout/latest/run.log
UVM_ERROR @ 13520401740 ps: (alert_handler_scoreboard.sv:483) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state
UVM_INFO @ 13520401740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 20 more failures.
9.alert_handler_lpg.71158180955138299778986107128671874232161661132652334196996725870446370983037
Line 87, in log /home/runner/_work/pavona/pavona/scratch/main/alert_handler_top_egret-sim-vcs/9.alert_handler_lpg/latest/run.log
UVM_ERROR @ 35530795635 ps: (alert_handler_scoreboard.sv:483) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state
UVM_INFO @ 35530795635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
22.alert_handler_lpg.17218001200769462219496896021419982865142942524808401679368106200616570862215
Line 88, in log /home/runner/_work/pavona/pavona/scratch/main/alert_handler_top_egret-sim-vcs/22.alert_handler_lpg/latest/run.log
UVM_ERROR @ 6078596694 ps: (alert_handler_scoreboard.sv:483) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (4 [0x4] vs 0 [0x0]) reg name: intr_state
UVM_INFO @ 6078596694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:1237) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 11 failures:
10.alert_handler_stress_all_with_rand_reset.84806143971959305535410758478865180900165068513532804502940899678335333817187
Line 108, in log /home/runner/_work/pavona/pavona/scratch/main/alert_handler_top_egret-sim-vcs/10.alert_handler_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 633763212 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 633763212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
19.alert_handler_stress_all_with_rand_reset.94336651742133453955366571744607540644926589798591460938015031795913141074629
Line 175, in log /home/runner/_work/pavona/pavona/scratch/main/alert_handler_top_egret-sim-vcs/19.alert_handler_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 10582129927 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 10582129927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 9 more failures.
UVM_ERROR (alert_handler_scoreboard.sv:595) [scoreboard] Check failed crashdump_val.loc_alert_cause[i] ==gmv(ral.loc_alert_cause[i]) (* [] vs * [])` has 8 failures:
15.alert_handler_ping_timeout.2054755229382126461539328792295527847335622300542590975389856545322822343576
Line 87, in log /home/runner/_work/pavona/pavona/scratch/main/alert_handler_top_egret-sim-vcs/15.alert_handler_ping_timeout/latest/run.log
UVM_ERROR @ 4180700717 ps: (alert_handler_scoreboard.sv:595) [uvm_test_top.env.scoreboard] Check failed crashdump_val.loc_alert_cause[i] == `gmv(ral.loc_alert_cause[i]) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 4180700717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
16.alert_handler_ping_timeout.103995312008253069743677585592839452200847815034819579196547000321750132430630
Line 87, in log /home/runner/_work/pavona/pavona/scratch/main/alert_handler_top_egret-sim-vcs/16.alert_handler_ping_timeout/latest/run.log
UVM_ERROR @ 38364741 ps: (alert_handler_scoreboard.sv:595) [uvm_test_top.env.scoreboard] Check failed crashdump_val.loc_alert_cause[i] == `gmv(ral.loc_alert_cause[i]) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 38364741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
UVM_ERROR (alert_handler_scoreboard.sv:487) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.loc_alert_cause_* has 2 failures:
Test alert_handler_lpg has 1 failures.
48.alert_handler_lpg.112723019066956224786339486929099343847104286610216111890520594201372372752372
Line 87, in log /home/runner/_work/pavona/pavona/scratch/main/alert_handler_top_egret-sim-vcs/48.alert_handler_lpg/latest/run.log
UVM_ERROR @ 47765234166 ps: (alert_handler_scoreboard.sv:487) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: alert_handler_reg_block.loc_alert_cause_0
UVM_INFO @ 47765234166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test alert_handler_entropy has 1 failures.
49.alert_handler_entropy.12069065469428560251751043042830055336648816371812925239765400754034551574665
Line 88, in log /home/runner/_work/pavona/pavona/scratch/main/alert_handler_top_egret-sim-vcs/49.alert_handler_entropy/latest/run.log
UVM_ERROR @ 323385512579 ps: (alert_handler_scoreboard.sv:487) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: alert_handler_reg_block.loc_alert_cause_0
UVM_INFO @ 323385512579 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:487) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classa_accum_cnt has 1 failures:
3.alert_handler_stress_all.62189772176533139105390057870815772830197559795246762627233972180314598440082
Line 108, in log /home/runner/_work/pavona/pavona/scratch/main/alert_handler_top_egret-sim-vcs/3.alert_handler_stress_all/latest/run.log
UVM_ERROR @ 44821955819 ps: (alert_handler_scoreboard.sv:487) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1313 [0x521] vs 1314 [0x522]) reg name: alert_handler_reg_block.classa_accum_cnt
UVM_INFO @ 44821955819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:487) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classd_accum_cnt has 1 failures:
7.alert_handler_lpg_stub_clk.40311942535563702038792037934913700220011721609253213360898016941150488305566
Line 87, in log /home/runner/_work/pavona/pavona/scratch/main/alert_handler_top_egret-sim-vcs/7.alert_handler_lpg_stub_clk/latest/run.log
UVM_ERROR @ 28466939140 ps: (alert_handler_scoreboard.sv:487) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1911 [0x777] vs 1912 [0x778]) reg name: alert_handler_reg_block.classd_accum_cnt
UVM_INFO @ 28466939140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:487) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classc_accum_cnt has 1 failures:
12.alert_handler_lpg.43693919418284926539732077059108246176056953258831548934572242285426249086879
Line 88, in log /home/runner/_work/pavona/pavona/scratch/main/alert_handler_top_egret-sim-vcs/12.alert_handler_lpg/latest/run.log
UVM_ERROR @ 99210428054 ps: (alert_handler_scoreboard.sv:487) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (202 [0xca] vs 201 [0xc9]) reg name: alert_handler_reg_block.classc_accum_cnt
UVM_INFO @ 99210428054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:258) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_a, is_local_err *, local_alert_type LocalEscIntFail has 1 failures:
16.alert_handler_sig_int_fail.94240078952738182433873903000381581514048136707416040103658247977009530563435
Line 92, in log /home/runner/_work/pavona/pavona/scratch/main/alert_handler_top_egret-sim-vcs/16.alert_handler_sig_int_fail/latest/run.log
UVM_ERROR @ 257586982 ps: (alert_handler_scoreboard.sv:258) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_a, is_local_err 1, local_alert_type LocalEscIntFail
UVM_INFO @ 257586982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1150) [alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
23.alert_handler_stress_all_with_rand_reset.110309419969366094318871641359223685702229475644588562782955640148957767781004
Line 308, in log /home/runner/_work/pavona/pavona/scratch/main/alert_handler_top_egret-sim-vcs/23.alert_handler_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5835599187 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 5835599187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (alert_handler_scoreboard.sv:258) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_c, is_local_err *, local_alert_type LocalAlertIntFail has 1 failures:
35.alert_handler_entropy.22852737559647940972014701681644431911541019143151766229509279136707284643996
Line 87, in log /home/runner/_work/pavona/pavona/scratch/main/alert_handler_top_egret-sim-vcs/35.alert_handler_entropy/latest/run.log
UVM_ERROR @ 28795570299 ps: (alert_handler_scoreboard.sv:258) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_c, is_local_err 0, local_alert_type LocalAlertIntFail
UVM_INFO @ 28795570299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---