AON_TIMER Simulation Results

Saturday June 06 2026 03:15:30 UTC

GitHub Revision: 285e653a0b

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.500s	576.058us	5	5	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	1.520s	985.695us	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	0.930s	521.615us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	16.140s	14.000ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.210s	511.548us	3	3	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	0.910s	316.712us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	0.930s	521.615us	20	20	100.00
		aon_timer_csr_aliasing	1.210s	511.548us	3	3	100.00
V1	mem_walk	aon_timer_mem_walk	0.960s	480.886us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.060s	501.977us	5	5	100.00
V1		TOTAL			68	68	100.00
V2	prescaler	aon_timer_prescaler	1.350s	705.776us	1	1	100.00
V2	jump	aon_timer_jump	1.250s	718.608us	3	3	100.00
V2	stress_all	aon_timer_stress_all	1.554m	105.101ms	6	6	100.00
V2	alert_test	aon_timer_alert_test	1.470s	457.329us	3	3	100.00
V2	intr_test	aon_timer_intr_test	1.000s	287.002us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	1.740s	424.186us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	1.740s	424.186us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	1.520s	985.695us	5	5	100.00
		aon_timer_csr_rw	0.930s	521.615us	20	20	100.00
		aon_timer_csr_aliasing	1.210s	511.548us	3	3	100.00
		aon_timer_same_csr_outstanding	2.730s	3.229ms	3	3	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	1.520s	985.695us	5	5	100.00
		aon_timer_csr_rw	0.930s	521.615us	20	20	100.00
		aon_timer_csr_aliasing	1.210s	511.548us	3	3	100.00
		aon_timer_same_csr_outstanding	2.730s	3.229ms	3	3	100.00
V2		TOTAL			86	86	100.00
V2S	tl_intg_err	aon_timer_sec_cm	5.030s	4.313ms	3	3	100.00
		aon_timer_tl_intg_err	8.050s	8.362ms	3	3	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	8.050s	8.362ms	3	3	100.00
V2S		TOTAL			6	6	100.00
V3	max_threshold	aon_timer_smoke_max_thold	1.700s	563.913us	5	5	100.00
V3	min_threshold	aon_timer_smoke_min_thold	1.480s	571.673us	5	5	100.00
V3	wkup_count_hi_cdc	aon_timer_wkup_count_cdc_hi	2.730s	3.350ms	3	3	100.00
V3	custom_intr	aon_timer_custom_intr	1.390s	455.359us	10	10	100.00
V3	alternating_on_off	aon_timer_alternating_enable_on_off	12.670s	4.160ms	6	6	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	24.160s	18.363ms	6	6	100.00
V3		TOTAL			35	35	100.00
		TOTAL			195	195	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	7	7	7	100.00
V2S	2	2	2	100.00
V3	6	6	6	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.65	99.09	99.05	98.53	--	98.56	96.67	100.00