285e653a0b| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | chip_sw_uart_tx_rx | chip_sw_uart_tx_rx | 0 | 0 | -- | ||
| V1 | chip_sw_uart_rx_overflow | chip_sw_uart_tx_rx | 0 | 0 | -- | ||
| V1 | chip_sw_uart_rand_baudrate | chip_sw_uart_rand_baudrate | 0 | 0 | -- | ||
| V1 | chip_sw_uart_tx_rx_alt_clk_freq | chip_sw_uart_tx_rx_alt_clk_freq | 0 | 0 | -- | ||
| V1 | chip_sw_gpio_out | chip_sw_gpio | 13.684s | 0 | 3 | 0.00 | |
| V1 | chip_sw_gpio_in | chip_sw_gpio | 13.684s | 0 | 3 | 0.00 | |
| V1 | chip_sw_gpio_irq | chip_sw_gpio | 13.684s | 0 | 3 | 0.00 | |
| V1 | chip_sw_example_tests | chip_sw_example_rom | 13.739s | 0 | 3 | 0.00 | |
| chip_sw_example_manufacturer | 13.749s | 0 | 3 | 0.00 | |||
| chip_sw_example_concurrency | 13.758s | 0 | 3 | 0.00 | |||
| chip_sw_example_flash | 0 | 0 | -- | ||||
| chip_sw_uart_smoketest_signed | 0 | 0 | -- | ||||
| V1 | csr_hw_reset | chip_csr_hw_reset | 0 | 0 | -- | ||
| V1 | csr_rw | chip_csr_rw | 0 | 0 | -- | ||
| V1 | csr_bit_bash | chip_csr_bit_bash | 10.790s | 0 | 3 | 0.00 | |
| V1 | csr_aliasing | chip_csr_aliasing | 9.880s | 0 | 3 | 0.00 | |
| V1 | csr_mem_rw_with_rand_reset | chip_csr_mem_rw_with_rand_reset | 0 | 0 | -- | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | chip_csr_aliasing | 9.880s | 0 | 3 | 0.00 | |
| chip_csr_rw | 0 | 0 | -- | ||||
| V1 | xbar_smoke | xbar_smoke | 38.120s | 62.398us | 100 | 100 | 100.00 |
| V1 | TOTAL | 100 | 118 | 84.75 | |||
| V2 | chip_sw_spi_device_flash_mode | chip_sw_uart_tx_rx_bootstrap | 0 | 0 | -- | ||
| V2 | chip_sw_spi_device_pass_through | chip_sw_spi_device_pass_through | 13.634s | 0 | 3 | 0.00 | |
| V2 | chip_sw_spi_device_pass_through_collision | chip_sw_spi_device_pass_through_collision | 14.728s | 0 | 3 | 0.00 | |
| V2 | chip_sw_spi_device_tpm | chip_sw_spi_device_tpm | 0 | 0 | -- | ||
| V2 | chip_sw_spi_host_tx_rx | chip_sw_spi_host_tx_rx | 0 | 0 | -- | ||
| V2 | chip_sw_i2c_host_tx_rx | chip_sw_i2c_host_tx_rx | 0 | 0 | -- | ||
| V2 | chip_sw_i2c_device_tx_rx | chip_sw_i2c_device_tx_rx | 0 | 0 | -- | ||
| V2 | chip_pin_mux | chip_padctrl_attributes | 3.360s | 0 | 10 | 0.00 | |
| V2 | chip_padctrl_attributes | chip_padctrl_attributes | 3.360s | 0 | 10 | 0.00 | |
| V2 | chip_sw_sleep_pin_mio_dio_val | chip_sw_sleep_pin_mio_dio_val | 0 | 0 | -- | ||
| V2 | chip_sw_sleep_pin_wake | chip_sw_sleep_pin_wake | 0 | 0 | -- | ||
| V2 | chip_sw_sleep_pin_retention | chip_sw_sleep_pin_retention | 0 | 0 | -- | ||
| V2 | chip_sw_mbx_smoke | chip_sw_mbx_smoke | 0 | 0 | -- | ||
| V2 | chip_sw_data_integrity | chip_sw_data_integrity_escalation | 0 | 0 | -- | ||
| V2 | chip_sw_instruction_integrity | chip_sw_data_integrity_escalation | 0 | 0 | -- | ||
| V2 | chip_jtag_csr_rw | chip_jtag_csr_rw | 1.695m | 117.002us | 0 | 3 | 0.00 |
| V2 | chip_jtag_mem_access | chip_jtag_mem_access | 1.624m | 117.009us | 0 | 3 | 0.00 |
| V2 | chip_rv_dm_ndm_reset_req | chip_rv_dm_ndm_reset_req | 13.824s | 0 | 3 | 0.00 | |
| V2 | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 0 | 0 | -- | ||
| V2 | chip_rv_dm_access_after_wakeup | chip_sw_rv_dm_access_after_wakeup | 0 | 0 | -- | ||
| V2 | chip_rv_dm_lc_disabled | chip_rv_dm_lc_disabled | 14.120m | 1.019ms | 2 | 3 | 66.67 |
| V2 | chip_sw_timer | chip_sw_rv_timer_irq | 13.473s | 0 | 3 | 0.00 | |
| V2 | chip_sw_aon_timer_wakeup_irq | chip_sw_aon_timer_irq | 14.670s | 0 | 3 | 0.00 | |
| V2 | chip_sw_aon_timer_sleep_wakeup | chip_sw_pwrmgr_smoketest | 0 | 0 | -- | ||
| V2 | chip_sw_aon_timer_wdog_bark_irq | chip_sw_aon_timer_irq | 14.670s | 0 | 3 | 0.00 | |
| V2 | chip_sw_aon_timer_wdog_lc_escalate | chip_sw_aon_timer_wdog_lc_escalate | 14.846s | 0 | 3 | 0.00 | |
| V2 | chip_sw_aon_timer_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 14.470s | 0 | 3 | 0.00 | |
| V2 | chip_sw_aon_timer_sleep_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 14.470s | 0 | 3 | 0.00 | |
| V2 | chip_sw_aon_timer_sleep_wdog_sleep_pause | chip_sw_aon_timer_sleep_wdog_sleep_pause | 14.807s | 0 | 5 | 0.00 | |
| V2 | chip_sw_plic_all_irqs | chip_plic_all_irqs | 0 | 0 | -- | ||
| V2 | chip_sw_plic_sw_irq | chip_sw_plic_sw_irq | 14.798s | 0 | 3 | 0.00 | |
| V2 | chip_sw_clkmgr_idle_trans | chip_sw_acc_randomness | 14.521s | 0 | 3 | 0.00 | |
| chip_sw_aes_idle | 13.772s | 0 | 3 | 0.00 | |||
| chip_sw_hmac_enc_idle | 13.952s | 0 | 3 | 0.00 | |||
| chip_sw_kmac_idle | 14.067s | 0 | 3 | 0.00 | |||
| V2 | chip_sw_clkmgr_off_trans | chip_sw_clkmgr_off_aes_trans | 13.610s | 0 | 3 | 0.00 | |
| chip_sw_clkmgr_off_hmac_trans | 14.080s | 0 | 3 | 0.00 | |||
| chip_sw_clkmgr_off_kmac_trans | 14.108s | 0 | 3 | 0.00 | |||
| chip_sw_clkmgr_off_acc_trans | 13.673s | 0 | 3 | 0.00 | |||
| V2 | chip_sw_clkmgr_off_peri | chip_sw_clkmgr_off_peri | 0 | 0 | -- | ||
| V2 | chip_sw_clkmgr_jitter | chip_sw_acc_ecdsa_op_irq_jitter_en | 14.567s | 0 | 3 | 0.00 | |
| chip_sw_aes_enc_jitter_en | 14.498s | 0 | 3 | 0.00 | |||
| chip_sw_hmac_enc_jitter_en | 14.044s | 0 | 3 | 0.00 | |||
| chip_sw_keymgr_dpe_key_derivation_jitter_en | 14.021s | 0 | 3 | 0.00 | |||
| chip_sw_kmac_mode_kmac_jitter_en | 14.016s | 0 | 3 | 0.00 | |||
| chip_sw_clkmgr_jitter | 13.965s | 0 | 3 | 0.00 | |||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 0 | 0 | -- | ||||
| chip_sw_edn_entropy_reqs_jitter | 0 | 0 | -- | ||||
| V2 | chip_sw_clkmgr_extended_range | chip_sw_clkmgr_jitter_reduced_freq | 13.834s | 0 | 3 | 0.00 | |
| chip_sw_acc_ecdsa_op_irq_jitter_en_reduced_freq | 13.762s | 0 | 3 | 0.00 | |||
| chip_sw_aes_enc_jitter_en_reduced_freq | 13.770s | 0 | 3 | 0.00 | |||
| chip_sw_hmac_enc_jitter_en_reduced_freq | 13.794s | 0 | 3 | 0.00 | |||
| chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq | 13.814s | 0 | 3 | 0.00 | |||
| chip_sw_kmac_mode_kmac_jitter_en_reduced_freq | 14.727s | 0 | 3 | 0.00 | |||
| chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq | 14.754s | 0 | 3 | 0.00 | |||
| chip_sw_csrng_edn_concurrency_reduced_freq | 14.871s | 0 | 3 | 0.00 | |||
| V2 | chip_sw_clkmgr_deep_sleep_frequency | chip_sw_ast_clk_outputs | 0 | 0 | -- | ||
| V2 | chip_sw_clkmgr_sleep_frequency | chip_sw_clkmgr_sleep_frequency | 0 | 0 | -- | ||
| V2 | chip_sw_clkmgr_reset_frequency | chip_sw_clkmgr_reset_frequency | 0 | 0 | -- | ||
| V2 | chip_sw_clkmgr_escalation_reset | chip_sw_all_escalation_resets | 14.930s | 0 | 100 | 0.00 | |
| V2 | chip_sw_pwrmgr_external_full_reset | chip_sw_pwrmgr_full_aon_reset | 13.800s | 0 | 3 | 0.00 | |
| V2 | chip_sw_pwrmgr_random_sleep_all_wake_ups | chip_sw_pwrmgr_random_sleep_all_wake_ups | 0 | 0 | -- | ||
| V2 | chip_sw_pwrmgr_normal_sleep_all_wake_ups | chip_sw_pwrmgr_normal_sleep_all_wake_ups | 0 | 0 | -- | ||
| V2 | chip_sw_pwrmgr_sleep_all_reset_reqs | chip_sw_aon_timer_wdog_bite_reset | 14.470s | 0 | 3 | 0.00 | |
| V2 | chip_sw_pwrmgr_deep_sleep_all_wake_ups | chip_sw_pwrmgr_deep_sleep_all_wake_ups | 0 | 0 | -- | ||
| V2 | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 0 | 0 | -- | ||
| V2 | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | 0 | 0 | -- | ||
| V2 | chip_sw_pwrmgr_wdog_reset | chip_sw_pwrmgr_wdog_reset | 0 | 0 | -- | ||
| V2 | chip_sw_pwrmgr_aon_power_glitch_reset | chip_sw_pwrmgr_full_aon_reset | 13.800s | 0 | 3 | 0.00 | |
| V2 | chip_sw_pwrmgr_main_power_glitch_reset | chip_sw_pwrmgr_main_power_glitch_reset | 0 | 0 | -- | ||
| V2 | chip_sw_pwrmgr_random_sleep_power_glitch_reset | chip_sw_pwrmgr_random_sleep_power_glitch_reset | 0 | 0 | -- | ||
| V2 | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 0 | 0 | -- | ||
| V2 | chip_sw_pwrmgr_sleep_power_glitch_reset | chip_sw_pwrmgr_sleep_power_glitch_reset | 0 | 0 | -- | ||
| V2 | chip_sw_pwrmgr_random_sleep_all_reset_reqs | chip_sw_pwrmgr_random_sleep_all_reset_reqs | 0 | 0 | -- | ||
| V2 | chip_sw_pwrmgr_sleep_disabled | chip_sw_pwrmgr_sleep_disabled | 0 | 0 | -- | ||
| V2 | chip_sw_pwrmgr_escalation_reset | chip_sw_all_escalation_resets | 14.930s | 0 | 100 | 0.00 | |
| V2 | chip_sw_rstmgr_non_sys_reset_info | chip_sw_pwrmgr_smoketest | 0 | 0 | -- | ||
| V2 | chip_sw_rstmgr_sys_reset_info | chip_rv_dm_ndm_reset_req | 13.824s | 0 | 3 | 0.00 | |
| V2 | chip_sw_rstmgr_cpu_info | chip_sw_rstmgr_cpu_info | 13.741s | 0 | 3 | 0.00 | |
| V2 | chip_sw_rstmgr_sw_req_reset | chip_sw_rstmgr_sw_req | 13.688s | 0 | 3 | 0.00 | |
| V2 | chip_sw_rstmgr_alert_info | chip_sw_rstmgr_alert_info | 13.736s | 0 | 3 | 0.00 | |
| V2 | chip_sw_rstmgr_sw_rst | chip_sw_rstmgr_sw_rst | 13.712s | 0 | 3 | 0.00 | |
| V2 | chip_sw_rstmgr_escalation_reset | chip_sw_all_escalation_resets | 14.930s | 0 | 100 | 0.00 | |
| V2 | chip_sw_alert_handler_alerts | chip_sw_alert_test | 0 | 0 | -- | ||
| V2 | chip_sw_alert_handler_escalations | chip_sw_alert_handler_escalation | 0 | 0 | -- | ||
| V2 | chip_sw_all_escalation_resets | chip_sw_all_escalation_resets | 14.930s | 0 | 100 | 0.00 | |
| V2 | chip_sw_alert_handler_irqs | chip_plic_all_irqs | 0 | 0 | -- | ||
| V2 | chip_sw_alert_handler_entropy | chip_sw_alert_handler_entropy | 0 | 0 | -- | ||
| V2 | chip_sw_alert_handler_crashdump | chip_sw_rstmgr_alert_info | 13.736s | 0 | 3 | 0.00 | |
| V2 | chip_sw_alert_handler_ping_timeout | chip_sw_alert_handler_ping_timeout | 13.755s | 0 | 3 | 0.00 | |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_alerts | chip_sw_alert_handler_lpg_sleep_mode_alerts | 0 | 0 | -- | ||
| V2 | chip_sw_alert_handler_lpg_sleep_mode_pings | chip_sw_alert_handler_lpg_sleep_mode_pings | 0 | 0 | -- | ||
| V2 | chip_sw_alert_handler_lpg_clock_off | chip_sw_alert_handler_lpg_clkoff | 0 | 0 | -- | ||
| V2 | chip_sw_alert_handler_lpg_reset_toggle | chip_sw_alert_handler_lpg_reset_toggle | 0 | 0 | -- | ||
| V2 | chip_sw_alert_handler_reverse_ping_in_deep_sleep | chip_sw_alert_handler_reverse_ping_in_deep_sleep | 0 | 0 | -- | ||
| V2 | chip_sw_lc_ctrl_alert_handler_escalation | chip_sw_alert_handler_escalation | 0 | 0 | -- | ||
| V2 | chip_sw_lc_ctrl_jtag_access | chip_sw_lc_ctrl_transition | 0 | 0 | -- | ||
| V2 | chip_sw_lc_ctrl_otp_hw_cfg | chip_sw_lc_ctrl_otp_hw_cfg | 0 | 0 | -- | ||
| V2 | chip_sw_lc_ctrl_init | chip_sw_lc_ctrl_transition | 0 | 0 | -- | ||
| V2 | chip_sw_lc_ctrl_transitions | chip_sw_lc_ctrl_transition | 0 | 0 | -- | ||
| V2 | chip_sw_lc_ctrl_kmac_req | chip_sw_lc_ctrl_transition | 0 | 0 | -- | ||
| V2 | chip_sw_lc_ctrl_key_div | chip_sw_keymgr_dpe_key_derivation_prod | 13.998s | 0 | 3 | 0.00 | |
| V2 | chip_sw_lc_ctrl_broadcast | chip_sw_keymgr_dpe_key_derivation | 13.977s | 0 | 3 | 0.00 | |
| chip_sw_rom_ctrl_integrity_check | 14.054s | 0 | 3 | 0.00 | |||
| chip_prim_tl_access | 11.332m | 740.278us | 3 | 3 | 100.00 | ||
| chip_rv_dm_lc_disabled | 14.120m | 1.019ms | 2 | 3 | 66.67 | ||
| chip_sw_sram_ctrl_execution_main | 0 | 0 | -- | ||||
| chip_sw_lc_ctrl_transition | 0 | 0 | -- | ||||
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 0 | 0 | -- | ||||
| chip_sw_otp_ctrl_lc_signals_dev | 0 | 0 | -- | ||||
| chip_sw_otp_ctrl_lc_signals_prod | 0 | 0 | -- | ||||
| chip_sw_otp_ctrl_lc_signals_rma | 0 | 0 | -- | ||||
| V2 | chip_sw_aes_enc | chip_sw_aes_enc | 14.484s | 0 | 3 | 0.00 | |
| chip_sw_aes_enc_jitter_en | 14.498s | 0 | 3 | 0.00 | |||
| V2 | chip_sw_aes_entropy | chip_sw_aes_entropy | 13.780s | 0 | 3 | 0.00 | |
| V2 | chip_sw_aes_idle | chip_sw_aes_idle | 13.772s | 0 | 3 | 0.00 | |
| V2 | chip_sw_aes_sideload | chip_sw_keymgr_sideload_aes | 0 | 0 | -- | ||
| V2 | chip_sw_hmac_enc | chip_sw_hmac_enc | 14.043s | 0 | 3 | 0.00 | |
| chip_sw_hmac_enc_jitter_en | 14.044s | 0 | 3 | 0.00 | |||
| V2 | chip_sw_hmac_idle | chip_sw_hmac_enc_idle | 13.952s | 0 | 3 | 0.00 | |
| V2 | chip_sw_kmac_enc | chip_sw_kmac_mode_cshake | 14.780s | 0 | 3 | 0.00 | |
| chip_sw_kmac_mode_kmac | 13.993s | 0 | 3 | 0.00 | |||
| chip_sw_kmac_mode_kmac_jitter_en | 14.016s | 0 | 3 | 0.00 | |||
| V2 | chip_sw_kmac_app_keymgr | chip_sw_keymgr_dpe_key_derivation | 13.977s | 0 | 3 | 0.00 | |
| V2 | chip_sw_kmac_app_lc | chip_sw_lc_ctrl_transition | 0 | 0 | -- | ||
| V2 | chip_sw_kmac_app_rom | chip_sw_kmac_app_rom | 14.041s | 0 | 3 | 0.00 | |
| V2 | chip_sw_kmac_entropy | chip_sw_kmac_entropy | 14.276s | 0 | 3 | 0.00 | |
| V2 | chip_sw_kmac_idle | chip_sw_kmac_idle | 14.067s | 0 | 3 | 0.00 | |
| V2 | chip_sw_entropy_src_csrng | chip_sw_entropy_src_csrng | 15.740s | 0 | 3 | 0.00 | |
| V2 | chip_sw_csrng_edn_cmd | chip_sw_entropy_src_csrng | 15.740s | 0 | 3 | 0.00 | |
| V2 | chip_sw_csrng_fuse_en_sw_app_read | chip_sw_csrng_fuse_en_sw_app_read_test | 0 | 0 | -- | ||
| V2 | chip_sw_csrng_known_answer_tests | chip_sw_csrng_kat_test | 14.595s | 0 | 3 | 0.00 | |
| V2 | chip_sw_edn_entropy_reqs | chip_sw_csrng_edn_concurrency | 14.788s | 0 | 3 | 0.00 | |
| chip_sw_edn_entropy_reqs | 0 | 0 | -- | ||||
| V2 | chip_sw_keymgr_dpe_key_derivation | chip_sw_keymgr_dpe_key_derivation | 13.977s | 0 | 3 | 0.00 | |
| chip_sw_keymgr_dpe_key_derivation_jitter_en | 14.021s | 0 | 3 | 0.00 | |||
| V2 | chip_sw_keymgr_sideload_kmac | chip_sw_keymgr_sideload_kmac | 0 | 0 | -- | ||
| V2 | chip_sw_keymgr_sideload_aes | chip_sw_keymgr_sideload_aes | 0 | 0 | -- | ||
| V2 | chip_sw_keymgr_sideload_acc | chip_sw_keymgr_sideload_acc | 0 | 0 | -- | ||
| V2 | chip_sw_acc_op | chip_sw_acc_ecdsa_op_irq | 14.544s | 0 | 3 | 0.00 | |
| chip_sw_acc_ecdsa_op_irq_jitter_en | 14.567s | 0 | 3 | 0.00 | |||
| V2 | chip_sw_acc_rnd_entropy | chip_sw_acc_randomness | 14.521s | 0 | 3 | 0.00 | |
| V2 | chip_sw_acc_urnd_entropy | chip_sw_acc_randomness | 14.521s | 0 | 3 | 0.00 | |
| V2 | chip_sw_acc_idle | chip_sw_acc_randomness | 14.521s | 0 | 3 | 0.00 | |
| V2 | chip_sw_acc_mem_scramble | chip_sw_acc_mem_scramble | 14.590s | 0 | 3 | 0.00 | |
| V2 | chip_sw_rom_access | chip_sw_rom_ctrl_integrity_check | 14.054s | 0 | 3 | 0.00 | |
| V2 | chip_sw_rom_ctrl_integrity_check | chip_sw_rom_ctrl_integrity_check | 14.054s | 0 | 3 | 0.00 | |
| V2 | chip_sw_sram_scrambled_access | chip_sw_sram_ctrl_scrambled_access | 13.677s | 0 | 3 | 0.00 | |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 0 | 0 | -- | ||||
| V2 | chip_sw_sleep_sram_ret_contents | chip_sw_sleep_sram_ret_contents | 0 | 0 | -- | ||
| V2 | chip_sw_sram_execution | chip_sw_sram_ctrl_execution_main | 0 | 0 | -- | ||
| V2 | chip_sw_sram_lc_escalation | chip_sw_all_escalation_resets | 14.930s | 0 | 100 | 0.00 | |
| chip_sw_data_integrity_escalation | 0 | 0 | -- | ||||
| V2 | chip_otp_ctrl_init | chip_sw_lc_ctrl_transition | 0 | 0 | -- | ||
| V2 | chip_sw_otp_ctrl_keys | chip_sw_acc_mem_scramble | 14.590s | 0 | 3 | 0.00 | |
| chip_sw_keymgr_dpe_key_derivation | 13.977s | 0 | 3 | 0.00 | |||
| chip_sw_sram_ctrl_scrambled_access | 13.677s | 0 | 3 | 0.00 | |||
| chip_sw_rv_core_ibex_icache_invalidate | 13.744s | 0 | 3 | 0.00 | |||
| V2 | chip_sw_otp_ctrl_entropy | chip_sw_acc_mem_scramble | 14.590s | 0 | 3 | 0.00 | |
| chip_sw_keymgr_dpe_key_derivation | 13.977s | 0 | 3 | 0.00 | |||
| chip_sw_sram_ctrl_scrambled_access | 13.677s | 0 | 3 | 0.00 | |||
| chip_sw_rv_core_ibex_icache_invalidate | 13.744s | 0 | 3 | 0.00 | |||
| V2 | chip_sw_otp_ctrl_program | chip_sw_lc_ctrl_transition | 0 | 0 | -- | ||
| V2 | chip_sw_otp_ctrl_program_error | chip_sw_lc_ctrl_program_error | 0 | 0 | -- | ||
| V2 | chip_sw_otp_ctrl_hw_cfg | chip_sw_lc_ctrl_otp_hw_cfg | 0 | 0 | -- | ||
| V2 | chip_sw_otp_ctrl_lc_signals | chip_prim_tl_access | 11.332m | 740.278us | 3 | 3 | 100.00 |
| chip_sw_lc_ctrl_transition | 0 | 0 | -- | ||||
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 0 | 0 | -- | ||||
| chip_sw_otp_ctrl_lc_signals_dev | 0 | 0 | -- | ||||
| chip_sw_otp_ctrl_lc_signals_prod | 0 | 0 | -- | ||||
| chip_sw_otp_ctrl_lc_signals_rma | 0 | 0 | -- | ||||
| V2 | chip_sw_otp_prim_tl_access | chip_prim_tl_access | 11.332m | 740.278us | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_nvm_cnt | chip_sw_otp_ctrl_nvm_cnt | 0 | 0 | -- | ||
| V2 | chip_sw_otp_ctrl_sw_parts | chip_sw_otp_ctrl_sw_parts | 0 | 0 | -- | ||
| V2 | chip_sw_ast_clk_outputs | chip_sw_ast_clk_outputs | 0 | 0 | -- | ||
| V2 | chip_sw_ast_clk_rst_inputs | chip_sw_ast_clk_rst_inputs | 0 | 0 | -- | ||
| V2 | chip_sw_ast_sys_clk_jitter | chip_sw_acc_ecdsa_op_irq_jitter_en | 14.567s | 0 | 3 | 0.00 | |
| chip_sw_aes_enc_jitter_en | 14.498s | 0 | 3 | 0.00 | |||
| chip_sw_hmac_enc_jitter_en | 14.044s | 0 | 3 | 0.00 | |||
| chip_sw_keymgr_dpe_key_derivation_jitter_en | 14.021s | 0 | 3 | 0.00 | |||
| chip_sw_kmac_mode_kmac_jitter_en | 14.016s | 0 | 3 | 0.00 | |||
| chip_sw_clkmgr_jitter | 13.965s | 0 | 3 | 0.00 | |||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 0 | 0 | -- | ||||
| chip_sw_edn_entropy_reqs_jitter | 0 | 0 | -- | ||||
| V2 | chip_sw_ast_alerts | chip_sw_sensor_ctrl_alert | 0 | 0 | -- | ||
| V2 | chip_sw_sensor_ctrl_ast_alerts | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 0 | 0 | -- | ||
| chip_sw_sensor_ctrl_alert | 0 | 0 | -- | ||||
| V2 | chip_sw_sensor_ctrl_ast_status | chip_sw_sensor_ctrl_status | 0 | 0 | -- | ||
| V2 | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 0 | 0 | -- | ||
| V2 | chip_sw_soc_proxy_external_reset_requests | chip_sw_soc_proxy_smoketest | 13.497s | 0 | 3 | 0.00 | |
| V2 | chip_sw_soc_proxy_external_irqs | chip_sw_soc_proxy_smoketest | 13.497s | 0 | 3 | 0.00 | |
| V2 | chip_sw_soc_proxy_external_wakeup_requests | chip_sw_soc_proxy_external_wakeup | 13.780s | 0 | 3 | 0.00 | |
| V2 | chip_sw_soc_proxy_gpios | chip_sw_soc_proxy_gpios | 13.710s | 0 | 3 | 0.00 | |
| V2 | chip_sw_nmi_irq | chip_sw_rv_core_ibex_nmi_irq | 13.711s | 0 | 3 | 0.00 | |
| V2 | chip_sw_rv_core_ibex_rnd | chip_sw_rv_core_ibex_rnd | 14.613s | 0 | 3 | 0.00 | |
| V2 | chip_sw_rv_core_ibex_address_translation | chip_sw_rv_core_ibex_address_translation | 13.827s | 0 | 3 | 0.00 | |
| V2 | chip_sw_rv_core_ibex_icache_scrambled_access | chip_sw_rv_core_ibex_icache_invalidate | 13.744s | 0 | 3 | 0.00 | |
| V2 | chip_sw_rv_core_ibex_fault_dump | chip_sw_rstmgr_cpu_info | 13.741s | 0 | 3 | 0.00 | |
| V2 | chip_sw_rv_core_ibex_double_fault | chip_sw_rstmgr_cpu_info | 13.741s | 0 | 3 | 0.00 | |
| V2 | chip_sw_smoketest | chip_sw_aes_smoketest | 13.789s | 0 | 3 | 0.00 | |
| chip_sw_aon_timer_smoketest | 13.774s | 0 | 3 | 0.00 | |||
| chip_sw_clkmgr_smoketest | 13.767s | 0 | 3 | 0.00 | |||
| chip_sw_csrng_smoketest | 13.782s | 0 | 3 | 0.00 | |||
| chip_sw_gpio_smoketest | 14.761s | 0 | 3 | 0.00 | |||
| chip_sw_hmac_smoketest | 13.765s | 0 | 3 | 0.00 | |||
| chip_sw_kmac_smoketest | 13.787s | 0 | 3 | 0.00 | |||
| chip_sw_acc_smoketest | 13.785s | 0 | 3 | 0.00 | |||
| chip_sw_otp_ctrl_smoketest | 13.823s | 0 | 3 | 0.00 | |||
| chip_sw_rv_plic_smoketest | 13.772s | 0 | 3 | 0.00 | |||
| chip_sw_rv_timer_smoketest | 13.776s | 0 | 3 | 0.00 | |||
| chip_sw_rstmgr_smoketest | 13.774s | 0 | 3 | 0.00 | |||
| chip_sw_sram_ctrl_smoketest | 13.681s | 0 | 3 | 0.00 | |||
| chip_sw_uart_smoketest | 13.707s | 0 | 3 | 0.00 | |||
| chip_sw_pwrmgr_smoketest | 0 | 0 | -- | ||||
| V2 | chip_sw_rom_functests | rom_keymgr_functest | 0 | 0 | -- | ||
| V2 | chip_sw_signed | chip_sw_uart_smoketest_signed | 0 | 0 | -- | ||
| V2 | chip_sw_boot | chip_sw_uart_tx_rx_bootstrap | 0 | 0 | -- | ||
| V2 | chip_sw_secure_boot | base_rom_e2e_smoke | 13.765s | 0 | 3 | 0.00 | |
| V2 | chip_lc_scrap | chip_sw_lc_ctrl_rma_to_scrap | 13.167s | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_raw_to_scrap | 13.167s | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_test_locked0_to_scrap | 13.167s | 0 | 1 | 0.00 | |||
| chip_sw_lc_ctrl_rand_to_scrap | 13.730s | 0 | 3 | 0.00 | |||
| V2 | chip_lc_test_locked | chip_rv_dm_lc_disabled | 14.120m | 1.019ms | 2 | 3 | 66.67 |
| chip_sw_lc_walkthrough_testunlocks | 0 | 0 | -- | ||||
| V2 | chip_sw_lc_walkthrough | chip_sw_lc_walkthrough_dev | 0 | 0 | -- | ||
| chip_sw_lc_walkthrough_prod | 0 | 0 | -- | ||||
| chip_sw_lc_walkthrough_prodend | 0 | 0 | -- | ||||
| chip_sw_lc_walkthrough_rma | 0 | 0 | -- | ||||
| chip_sw_lc_walkthrough_testunlocks | 0 | 0 | -- | ||||
| V2 | chip_sw_lc_ctrl_volatile_raw_unlock | chip_sw_lc_ctrl_volatile_raw_unlock | 14.265s | 0 | 3 | 0.00 | |
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz | 14.766s | 0 | 3 | 0.00 | |||
| rom_volatile_raw_unlock | 0 | 0 | -- | ||||
| V2 | chip_sw_rom_raw_unlock | rom_raw_unlock | 0 | 0 | -- | ||
| V2 | chip_sw_exit_test_unlocked_bootstrap | chip_sw_exit_test_unlocked_bootstrap | 0 | 0 | -- | ||
| V2 | chip_sw_inject_scramble_seed | chip_sw_inject_scramble_seed | 0 | 0 | -- | ||
| V2 | tl_d_oob_addr_access | chip_tl_errors | 2.750s | 0 | 30 | 0.00 | |
| V2 | tl_d_illegal_access | chip_tl_errors | 2.750s | 0 | 30 | 0.00 | |
| V2 | tl_d_outstanding_access | chip_csr_aliasing | 9.880s | 0 | 3 | 0.00 | |
| chip_same_csr_outstanding | 10.400s | 0 | 3 | 0.00 | |||
| chip_csr_hw_reset | 0 | 0 | -- | ||||
| chip_csr_rw | 0 | 0 | -- | ||||
| V2 | tl_d_partial_access | chip_csr_aliasing | 9.880s | 0 | 3 | 0.00 | |
| chip_same_csr_outstanding | 10.400s | 0 | 3 | 0.00 | |||
| chip_csr_hw_reset | 0 | 0 | -- | ||||
| chip_csr_rw | 0 | 0 | -- | ||||
| V2 | xbar_base_random_sequence | xbar_random | 5.666m | 503.938us | 100 | 100 | 100.00 |
| V2 | xbar_random_delay | xbar_smoke_zero_delays | 14.780s | 12.838us | 100 | 100 | 100.00 |
| xbar_smoke_large_delays | 7.021m | 2.774ms | 100 | 100 | 100.00 | ||
| xbar_smoke_slow_rsp | 9.589m | 2.319ms | 100 | 100 | 100.00 | ||
| xbar_random_zero_delays | 2.385m | 74.932us | 100 | 100 | 100.00 | ||
| xbar_random_large_delays | 28.282m | 13.124ms | 100 | 100 | 100.00 | ||
| xbar_random_slow_rsp | 45.772m | 14.760ms | 100 | 100 | 100.00 | ||
| V2 | xbar_unmapped_address | xbar_unmapped_addr | 3.434m | 246.121us | 100 | 100 | 100.00 |
| xbar_error_and_unmapped_addr | 3.082m | 237.008us | 99 | 100 | 99.00 | ||
| V2 | xbar_error_cases | xbar_error_random | 4.419m | 487.475us | 100 | 100 | 100.00 |
| xbar_error_and_unmapped_addr | 3.082m | 237.008us | 99 | 100 | 99.00 | ||
| V2 | xbar_all_access_same_device | xbar_access_same_device | 9.434m | 931.930us | 100 | 100 | 100.00 |
| xbar_access_same_device_slow_rsp | 54.296m | 17.244ms | 66 | 100 | 66.00 | ||
| V2 | xbar_all_hosts_use_same_source_id | xbar_same_source | 4.469m | 491.588us | 100 | 100 | 100.00 |
| V2 | xbar_stress_all | xbar_stress_all | 49.062m | 4.204ms | 100 | 100 | 100.00 |
| xbar_stress_all_with_error | 40.530m | 4.124ms | 100 | 100 | 100.00 | ||
| V2 | xbar_stress_with_reset | xbar_stress_all_with_rand_reset | 53.337m | 4.737ms | 97 | 100 | 97.00 |
| xbar_stress_all_with_reset_error | 46.707m | 4.972ms | 97 | 100 | 97.00 | ||
| V2 | rom_e2e_smoke | rom_e2e_smoke | 0 | 0 | -- | ||
| V2 | rom_e2e_shutdown_output | rom_e2e_shutdown_output | 0 | 0 | -- | ||
| V2 | rom_e2e_shutdown_exception_c | rom_e2e_shutdown_exception_c | 0 | 0 | -- | ||
| V2 | rom_e2e_boot_policy_valid | rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 0 | 0 | -- | ||
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 0 | 0 | -- | ||||
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 0 | 0 | -- | ||||
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 0 | 0 | -- | ||||
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 0 | 0 | -- | ||||
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 0 | 0 | -- | ||||
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 0 | 0 | -- | ||||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 0 | 0 | -- | ||||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 0 | 0 | -- | ||||
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 0 | 0 | -- | ||||
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 0 | 0 | -- | ||||
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 0 | 0 | -- | ||||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 0 | 0 | -- | ||||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 0 | 0 | -- | ||||
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 0 | 0 | -- | ||||
| V2 | rom_e2e_sigverify_always | rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 0 | 0 | -- | ||
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 0 | 0 | -- | ||||
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 0 | 0 | -- | ||||
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 0 | 0 | -- | ||||
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 0 | 0 | -- | ||||
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 0 | 0 | -- | ||||
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 0 | 0 | -- | ||||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 0 | 0 | -- | ||||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 0 | 0 | -- | ||||
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 0 | 0 | -- | ||||
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 0 | 0 | -- | ||||
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 0 | 0 | -- | ||||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 0 | 0 | -- | ||||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 0 | 0 | -- | ||||
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 0 | 0 | -- | ||||
| V2 | rom_e2e_asm_init | rom_e2e_asm_init_test_unlocked0 | 0 | 0 | -- | ||
| rom_e2e_asm_init_dev | 0 | 0 | -- | ||||
| rom_e2e_asm_init_prod | 0 | 0 | -- | ||||
| rom_e2e_asm_init_prod_end | 0 | 0 | -- | ||||
| rom_e2e_asm_init_rma | 0 | 0 | -- | ||||
| V2 | rom_e2e_keymgr_init | rom_e2e_keymgr_init_rom_ext_meas | 0 | 0 | -- | ||
| rom_e2e_keymgr_init_rom_ext_no_meas | 0 | 0 | -- | ||||
| rom_e2e_keymgr_init_rom_ext_invalid_meas | 0 | 0 | -- | ||||
| V2 | rom_e2e_static_critical | rom_e2e_static_critical | 0 | 0 | -- | ||
| V2 | TOTAL | 1664 | 2094 | 79.47 | |||
| V2S | chip_sw_aes_masking_off | chip_sw_aes_masking_off | 14.508s | 0 | 3 | 0.00 | |
| V2S | chip_sw_rv_core_ibex_lockstep_glitch | chip_sw_rv_core_ibex_lockstep_glitch | 13.836s | 0 | 3 | 0.00 | |
| V2S | TOTAL | 0 | 6 | 0.00 | |||
| V3 | chip_sw_spi_device_pass_through_flash_model | chip_sw_spi_device_pass_through_flash_model | 0 | 0 | -- | ||
| V3 | chip_sw_spi_device_output_when_disabled_or_sleeping | chip_sw_spi_device_output_when_disabled_or_sleeping | 0 | 0 | -- | ||
| V3 | chip_rv_dm_perform_debug | rom_e2e_jtag_debug_test_unlocked0 | 0 | 0 | -- | ||
| rom_e2e_jtag_debug_dev | 0 | 0 | -- | ||||
| rom_e2e_jtag_debug_rma | 0 | 0 | -- | ||||
| V3 | chip_sw_rv_dm_access_after_hw_reset | chip_sw_rv_dm_access_after_escalation_reset | 0 | 0 | -- | ||
| V3 | chip_sw_plic_alerts | chip_sw_all_escalation_resets | 14.930s | 0 | 100 | 0.00 | |
| V3 | chip_sw_lc_ctrl_kmac_error | chip_sw_lc_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_csrng_edn_error | chip_sw_csrng_edn_error | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_sideload_kmac_error | chip_sw_keymgr_sideload_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_rom_ctrl_kmac_error | chip_sw_rom_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_otp_ctrl_vendor_test_csr_access | chip_sw_otp_ctrl_vendor_test_csr_access | 0 | 0 | -- | ||
| V3 | chip_sw_otp_ctrl_escalation | chip_sw_otp_ctrl_escalation | 13.167s | 0 | 1 | 0.00 | |
| V3 | chip_sw_rv_core_ibex_alerts | chip_sw_rv_core_ibex_alerts | 0 | 0 | -- | ||
| V3 | chip_sw_coremark | chip_sw_coremark | 0 | 0 | -- | ||
| V3 | chip_sw_power_max_load | chip_sw_power_virus | 0 | 0 | -- | ||
| V3 | rom_e2e_debug | rom_e2e_jtag_debug_test_unlocked0 | 0 | 0 | -- | ||
| rom_e2e_jtag_debug_dev | 0 | 0 | -- | ||||
| rom_e2e_jtag_debug_rma | 0 | 0 | -- | ||||
| V3 | rom_e2e_jtag_inject | rom_e2e_jtag_inject_test_unlocked0 | 0 | 0 | -- | ||
| rom_e2e_jtag_inject_dev | 0 | 0 | -- | ||||
| rom_e2e_jtag_inject_rma | 0 | 0 | -- | ||||
| V3 | rom_bootstrap_rma | rom_bootstrap_rma | 0 | 0 | -- | ||
| V3 | rom_e2e_weak_straps | rom_e2e_weak_straps | 0 | 0 | -- | ||
| V3 | rom_e2e_self_hash | rom_e2e_self_hash | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 1 | 0.00 | |||
| Unmapped tests | chip_sw_rstmgr_rst_cnsty_escalation | 14.713s | 0 | 3 | 0.00 | ||
| chip_sw_entropy_src_kat_test | 14.039s | 0 | 3 | 0.00 | |||
| chip_sw_entropy_src_ast_rng_req | 14.014s | 0 | 3 | 0.00 | |||
| chip_plic_all_irqs_0 | 14.762s | 0 | 3 | 0.00 | |||
| chip_plic_all_irqs_10 | 15.817s | 0 | 3 | 0.00 | |||
| chip_sw_dma_inline_hashing | 13.590s | 0 | 3 | 0.00 | |||
| chip_sw_dma_abort | 13.742s | 0 | 3 | 0.00 | |||
| chip_sw_entropy_src_smoketest | 14.735s | 0 | 3 | 0.00 | |||
| chip_sw_mbx_smoketest | 14.773s | 0 | 3 | 0.00 | |||
| TOTAL | 1764 | 2246 | 78.54 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 9 | 9 | 0 | 0.00 |
| V1 | 15 | 7 | 1 | 6.67 |
| V2 | 218 | 106 | 14 | 6.42 |
| V2S | 2 | 2 | 0 | 0.00 |
| V3 | 21 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 43.11 | 46.77 | 45.07 | 36.15 | 0.00 | 45.60 | 45.40 | 82.80 |
Job returned non-zero exit code has 386 failures:
0.chip_sw_example_rom.11660562445357366328014627578827643253644572711600717656239721713178988509821
Log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_example_rom/latest/run.log
cquery_common_opts=['--ui_event_filters=-info', '--noshow_progress', '--//hw/top=dragonfly', '--//hw/top=dragonfly']
INFO: [build_sw_collateral_for_sim.py:202] cquery_cmd = ./bazelisk.sh cquery //sw/device/tests:example_test_from_rom_sim_dv --ui_event_filters=-info --noshow_progress --//hw/top=dragonfly --//hw/top=dragonfly --output=label_kind
---- STDOUT ----
---- STDERR ----
ERROR: Error while parsing 'release 8.10 (Cerulean Leopard) //sw/device/tests:example_test_from_rom_sim_dv': unexpected token '8.10' after query expression 'release'
_run_cmd -> had a non-zero return code of 2.
make: *** [/home/runner/_work/pavona/pavona/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
1.chip_sw_example_rom.10107890946311752155595760799513209403580985362202721894559937885547897200970
Log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/1.chip_sw_example_rom/latest/run.log
cquery_common_opts=['--ui_event_filters=-info', '--noshow_progress', '--//hw/top=dragonfly', '--//hw/top=dragonfly']
INFO: [build_sw_collateral_for_sim.py:202] cquery_cmd = ./bazelisk.sh cquery //sw/device/tests:example_test_from_rom_sim_dv --ui_event_filters=-info --noshow_progress --//hw/top=dragonfly --//hw/top=dragonfly --output=label_kind
---- STDOUT ----
---- STDERR ----
ERROR: Error while parsing 'release 8.10 (Cerulean Leopard) //sw/device/tests:example_test_from_rom_sim_dv': unexpected token '8.10' after query expression 'release'
_run_cmd -> had a non-zero return code of 2.
make: *** [/home/runner/_work/pavona/pavona/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
... and 1 more failures.
0.chip_sw_example_manufacturer.20367347170285114384836354012442865300803836983857592973390152855925501664122
Log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log
INFO: [build_sw_collateral_for_sim.py:202] cquery_cmd = ./bazelisk.sh cquery @manufacturer_test_hooks//:example_test_sim_dv --ui_event_filters=-info --noshow_progress --//hw/top=dragonfly --//hw/top=dragonfly --output=label_kind
---- STDOUT ----
---- STDERR ----
Another command (pid=3172044) is running. Waiting for it to complete on the server (server_pid=2746178)...
ERROR: Error while parsing 'release 8.10 (Cerulean Leopard) @manufacturer_test_hooks//:example_test_sim_dv': unexpected token '8.10' after query expression 'release'
_run_cmd -> had a non-zero return code of 2.
make: *** [/home/runner/_work/pavona/pavona/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
1.chip_sw_example_manufacturer.68485012333400197392100888605046196631270886525203741975787907818973734869232
Log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/1.chip_sw_example_manufacturer/latest/run.log
cquery_common_opts=['--ui_event_filters=-info', '--noshow_progress', '--//hw/top=dragonfly', '--//hw/top=dragonfly']
INFO: [build_sw_collateral_for_sim.py:202] cquery_cmd = ./bazelisk.sh cquery @manufacturer_test_hooks//:example_test_sim_dv --ui_event_filters=-info --noshow_progress --//hw/top=dragonfly --//hw/top=dragonfly --output=label_kind
---- STDOUT ----
---- STDERR ----
ERROR: Error while parsing 'release 8.10 (Cerulean Leopard) @manufacturer_test_hooks//:example_test_sim_dv': unexpected token '8.10' after query expression 'release'
_run_cmd -> had a non-zero return code of 2.
make: *** [/home/runner/_work/pavona/pavona/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
... and 1 more failures.
0.chip_sw_example_concurrency.7461036633746837070716661991914276883413605793941573079705087885176742800002
Log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_example_concurrency/latest/run.log
cquery_common_opts=['--ui_event_filters=-info', '--noshow_progress', '--//hw/top=dragonfly', '--//hw/top=dragonfly']
INFO: [build_sw_collateral_for_sim.py:202] cquery_cmd = ./bazelisk.sh cquery //sw/device/tests:example_concurrency_test_sim_dv --ui_event_filters=-info --noshow_progress --//hw/top=dragonfly --//hw/top=dragonfly --output=label_kind
---- STDOUT ----
---- STDERR ----
ERROR: Error while parsing 'release 8.10 (Cerulean Leopard) //sw/device/tests:example_concurrency_test_sim_dv': unexpected token '8.10' after query expression 'release'
_run_cmd -> had a non-zero return code of 2.
make: *** [/home/runner/_work/pavona/pavona/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
1.chip_sw_example_concurrency.63801503152821617395443668966354853417077229371823304027856024208845260302824
Log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/1.chip_sw_example_concurrency/latest/run.log
cquery_common_opts=['--ui_event_filters=-info', '--noshow_progress', '--//hw/top=dragonfly', '--//hw/top=dragonfly']
INFO: [build_sw_collateral_for_sim.py:202] cquery_cmd = ./bazelisk.sh cquery //sw/device/tests:example_concurrency_test_sim_dv --ui_event_filters=-info --noshow_progress --//hw/top=dragonfly --//hw/top=dragonfly --output=label_kind
---- STDOUT ----
---- STDERR ----
ERROR: Error while parsing 'release 8.10 (Cerulean Leopard) //sw/device/tests:example_concurrency_test_sim_dv': unexpected token '8.10' after query expression 'release'
_run_cmd -> had a non-zero return code of 2.
make: *** [/home/runner/_work/pavona/pavona/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
... and 1 more failures.
0.chip_sw_all_escalation_resets.19395592927062204478820363072022327480576801448746141861276903642174806731560
Log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_all_escalation_resets/latest/run.log
INFO: [build_sw_collateral_for_sim.py:202] cquery_cmd = ./bazelisk.sh cquery //sw/device/tests/sim_dv:all_escalation_resets_test_sim_dv --ui_event_filters=-info --noshow_progress --//hw/top=dragonfly --//hw/top=dragonfly --output=label_kind
---- STDOUT ----
---- STDERR ----
Another command (pid=3173276) is running. Waiting for it to complete on the server (server_pid=2746178)...
ERROR: Error while parsing 'release 8.10 (Cerulean Leopard) //sw/device/tests/sim_dv:all_escalation_resets_test_sim_dv': unexpected token '8.10' after query expression 'release'
_run_cmd -> had a non-zero return code of 2.
make: *** [/home/runner/_work/pavona/pavona/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
1.chip_sw_all_escalation_resets.35959675574268910955661258432201930672237902054315328796800529524735301772726
Log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/1.chip_sw_all_escalation_resets/latest/run.log
cquery_common_opts=['--ui_event_filters=-info', '--noshow_progress', '--//hw/top=dragonfly', '--//hw/top=dragonfly']
INFO: [build_sw_collateral_for_sim.py:202] cquery_cmd = ./bazelisk.sh cquery //sw/device/tests/sim_dv:all_escalation_resets_test_sim_dv --ui_event_filters=-info --noshow_progress --//hw/top=dragonfly --//hw/top=dragonfly --output=label_kind
---- STDOUT ----
---- STDERR ----
ERROR: Error while parsing 'release 8.10 (Cerulean Leopard) //sw/device/tests/sim_dv:all_escalation_resets_test_sim_dv': unexpected token '8.10' after query expression 'release'
_run_cmd -> had a non-zero return code of 2.
make: *** [/home/runner/_work/pavona/pavona/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
... and 98 more failures.
0.chip_sw_rstmgr_rst_cnsty_escalation.109863546761150496126139795158919975636248176523924086772643659533732276501917
Log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_rstmgr_rst_cnsty_escalation/latest/run.log
INFO: [build_sw_collateral_for_sim.py:202] cquery_cmd = ./bazelisk.sh cquery //sw/device/tests/sim_dv:all_escalation_resets_test_sim_dv --ui_event_filters=-info --noshow_progress --//hw/top=dragonfly --//hw/top=dragonfly --output=label_kind
---- STDOUT ----
---- STDERR ----
Another command (pid=3172250) is running. Waiting for it to complete on the server (server_pid=2746178)...
ERROR: Error while parsing 'release 8.10 (Cerulean Leopard) //sw/device/tests/sim_dv:all_escalation_resets_test_sim_dv': unexpected token '8.10' after query expression 'release'
_run_cmd -> had a non-zero return code of 2.
make: *** [/home/runner/_work/pavona/pavona/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
1.chip_sw_rstmgr_rst_cnsty_escalation.27927669769333332839974704853579734984160559048318916405486824804015164425878
Log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/1.chip_sw_rstmgr_rst_cnsty_escalation/latest/run.log
cquery_common_opts=['--ui_event_filters=-info', '--noshow_progress', '--//hw/top=dragonfly', '--//hw/top=dragonfly']
INFO: [build_sw_collateral_for_sim.py:202] cquery_cmd = ./bazelisk.sh cquery //sw/device/tests/sim_dv:all_escalation_resets_test_sim_dv --ui_event_filters=-info --noshow_progress --//hw/top=dragonfly --//hw/top=dragonfly --output=label_kind
---- STDOUT ----
---- STDERR ----
ERROR: Error while parsing 'release 8.10 (Cerulean Leopard) //sw/device/tests/sim_dv:all_escalation_resets_test_sim_dv': unexpected token '8.10' after query expression 'release'
_run_cmd -> had a non-zero return code of 2.
make: *** [/home/runner/_work/pavona/pavona/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
... and 1 more failures.
Job timed out after * minutes has 40 failures:
2.xbar_access_same_device_slow_rsp.64311968437949264056648948395458060867028601192009754208330651285912411553710
Log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/2.xbar_access_same_device_slow_rsp/latest/run.log
Job timed out after 60 minutes
3.xbar_access_same_device_slow_rsp.39232001543476979948671592260045508520796527775475537128258359543989933435438
Log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/3.xbar_access_same_device_slow_rsp/latest/run.log
Job timed out after 60 minutes
... and 32 more failures.
19.xbar_stress_all_with_reset_error.18571012064063982737899111151130846986711781923849468953345312460131448464777
Log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/19.xbar_stress_all_with_reset_error/latest/run.log
Job timed out after 60 minutes
33.xbar_stress_all_with_reset_error.4196349091875427281280166671849199548514145305798094882638951754796090032751
Log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/33.xbar_stress_all_with_reset_error/latest/run.log
Job timed out after 60 minutes
... and 1 more failures.
54.xbar_stress_all_with_rand_reset.106892897048051601977621979612554530621844110308626773596230947560463954800579
Log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/54.xbar_stress_all_with_rand_reset/latest/run.log
Job timed out after 60 minutes
66.xbar_stress_all_with_rand_reset.95524741210648769964853212989658143265837034436887942049697599389746776002754
Log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/66.xbar_stress_all_with_rand_reset/latest/run.log
Job timed out after 60 minutes
... and 1 more failures.
UVM_WARNING @ * us: [BDTYP] Cannot create an object of type 'chip_dragonfly_common_vseq' because it is not registered with the factory. has 30 failures:
0.chip_tl_errors.18094730988368792727068319308695097440757826160933983266196351749769484854055
Line 220, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_tl_errors/latest/run.log
UVM_WARNING @ 0.000000 us: [BDTYP] Cannot create an object of type 'chip_dragonfly_common_vseq' because it is not registered with the factory.
UVM_INFO @ 0.000000 us: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
1.chip_tl_errors.75410308948372889853445778101552460633197379732556638994367821426788073095131
Line 220, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/1.chip_tl_errors/latest/run.log
UVM_WARNING @ 0.000000 us: [BDTYP] Cannot create an object of type 'chip_dragonfly_common_vseq' because it is not registered with the factory.
UVM_INFO @ 0.000000 us: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
... and 28 more failures.
Error-[CNST-CIF] Constraints inconsistency failure has 10 failures:
0.chip_padctrl_attributes.22239409964266326962610452204460835753219373327973125235898081089056455700104
Line 292, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_padctrl_attributes/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 92
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
1.chip_padctrl_attributes.84952983333064681312825946358665079742209084020270570357725795335402009292762
Line 292, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/1.chip_padctrl_attributes/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 92
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
... and 8 more failures.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 9 failures:
0.chip_csr_bit_bash.93288510997504209443050599462011780718572505657299601036871051106996118815685
Line 142, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_csr_bit_bash/latest/run.log
UVM_FATAL @ 0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_csr_bit_bash.57770210302968254736488697568263645472527170164182244492990305768044766779346
Line 142, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/1.chip_csr_bit_bash/latest/run.log
UVM_FATAL @ 0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_csr_aliasing.8200996569639604486992105705732818521637270474870251284981785564131908365941
Line 142, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_csr_aliasing/latest/run.log
UVM_FATAL @ 0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_csr_aliasing.37920889379958460551340307811945087013677632549885675173009331843290599796996
Line 142, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/1.chip_csr_aliasing/latest/run.log
UVM_FATAL @ 0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_same_csr_outstanding.45331907247869988631904174120340288530946135918753149874422831788118034273979
Line 142, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
UVM_FATAL @ 0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_same_csr_outstanding.95936471413074660484439519091419246826344561414916630297113201843339560136160
Line 142, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/1.chip_same_csr_outstanding/latest/run.log
UVM_FATAL @ 0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@41855) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 6 failures:
0.chip_jtag_csr_rw.95229317579735430128898251584594633788278541674177270591491050609011008412414
Line 5980, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_jtag_csr_rw/latest/run.log
UVM_ERROR @ 116.993000 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@41855) { a_addr: 'h30480000 a_data: 'hc59730c3 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1 a_opcode: 'h0 a_user: 'h2696c d_param: 'h0 d_source: 'h1 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 116.993000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_jtag_csr_rw.108247619143570744379679145821244810285054355983963486680945630027240973344217
Line 5980, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/1.chip_jtag_csr_rw/latest/run.log
UVM_ERROR @ 117.029000 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@41855) { a_addr: 'h30480000 a_data: 'hca07c460 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h29 a_opcode: 'h1 a_user: 'h248b4 d_param: 'h0 d_source: 'h29 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 117.029000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_jtag_mem_access.67684333227821308994511322635129845650784047741249383587873589234841805297747
Line 5980, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_jtag_mem_access/latest/run.log
UVM_ERROR @ 117.024000 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@41855) { a_addr: 'h30480000 a_data: 'hcb6cbc43 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h37 a_opcode: 'h0 a_user: 'h2690a d_param: 'h0 d_source: 'h37 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 117.024000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_jtag_mem_access.17811166531057042058776079503330246757027073523568703768585124090716801792964
Line 5980, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/1.chip_jtag_mem_access/latest/run.log
UVM_ERROR @ 117.009000 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@41855) { a_addr: 'h30480000 a_data: 'h1cb61d30 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2e a_opcode: 'h1 a_user: 'h248aa d_param: 'h0 d_source: 'h2e d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 117.009000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (chip_rv_dm_lc_disabled_vseq.sv:73) [chip_rv_dm_lc_disabled_vseq] Check failed dmcontrol == * (* [*] vs * [*]) Writes to dmcontrol must be gated in this LC state has 1 failures:
0.chip_rv_dm_lc_disabled.72633318798661837611941119907471783463818941958262036191961931713307044378573
Line 210, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log
UVM_ERROR @ 124.792088 us: (chip_rv_dm_lc_disabled_vseq.sv:73) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed dmcontrol == 0 (1 [0x1] vs 0 [0x0]) Writes to dmcontrol must be gated in this LC state
UVM_INFO @ 124.792088 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---