CHIP_EGRET Simulation Results

Saturday June 06 2026 03:15:30 UTC

GitHub Revision: `285e653a0b`

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
	crypto_lib_hash_stress	crypto_lib_hash_stress			0	0	--
	crypto_lib_ecc_stress	crypto_lib_ecc_stress			0	0	--
	crypto_lib_rsa_key_gen_stress	crypto_lib_rsa_key_gen_stress			0	0	--
	crypto_lib_rsa_stress	crypto_lib_rsa_stress			0	0	--
	crypto_lib_aes_stress	crypto_lib_aes_stress			0	0	--
	crypto_lib_symmetric_keygen	crypto_lib_symmetric_keygen			0	0	--
	crypto_lib_entropy	crypto_lib_entropy			0	0	--
V1	chip_sw_example_tests	chip_sw_example_flash	13.519s		0	3	0.00
		chip_sw_example_rom	13.519s		0	3	0.00
		chip_sw_example_manufacturer	13.496s		0	3	0.00
		chip_sw_example_concurrency	12.383s		0	3	0.00
V1	csr_hw_reset	chip_csr_hw_reset			0	0	--
V1	csr_rw	chip_csr_rw			0	0	--
V1	csr_bit_bash	chip_csr_bit_bash	5.520s		0	3	0.00
V1	csr_aliasing	chip_csr_aliasing	5.250s		0	3	0.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset			0	0	--
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	5.250s		0	3	0.00
		chip_csr_rw			0	0	--
V1	xbar_smoke	xbar_smoke	9.080s	263.759us	100	100	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	12.253s		0	3	0.00
V1	chip_sw_gpio_in	chip_sw_gpio	12.253s		0	3	0.00
V1	chip_sw_gpio_irq	chip_sw_gpio	12.253s		0	3	0.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	12.403s		0	5	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	12.403s		0	5	0.00
		chip_sw_uart_tx_rx_idx1	13.197s		0	5	0.00
		chip_sw_uart_tx_rx_idx2	13.200s		0	5	0.00
		chip_sw_uart_tx_rx_idx3	13.396s		0	5	0.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	13.194s		0	20	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	12.369s		0	5	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	12.312s		0	5	0.00
V1		TOTAL			100	171	58.48
V2	chip_pin_mux	chip_padctrl_attributes	4.335m	5.372ms	10	10	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	4.335m	5.372ms	10	10	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	12.808s		0	3	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	12.808s		0	3	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	12.454s		0	3	0.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	12.293s		0	5	0.00
		chip_tap_straps_testunlock0	13.053s		0	5	0.00
		chip_tap_straps_rma	12.342s		0	5	0.00
		chip_tap_straps_prod	12.367s		0	5	0.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	12.448s		0	3	0.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	12.505s		0	3	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	13.196s		0	6	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	13.196s		0	6	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	12.314s		0	3	0.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	12.287s		0	3	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	12.269s		0	3	0.00
		chip_sw_flash_ctrl_access_jitter_en	12.366s		0	3	0.00
		chip_sw_acc_ecdsa_op_irq_jitter_en	12.253s		0	3	0.00
		chip_sw_aes_enc_jitter_en	12.396s		0	3	0.00
		chip_sw_edn_entropy_reqs_jitter	12.317s		0	3	0.00
		chip_sw_hmac_enc_jitter_en	12.923s		0	3	0.00
		chip_sw_keymgr_key_derivation_jitter_en	12.388s		0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en	12.352s		0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.861s		0	3	0.00
		chip_sw_clkmgr_jitter	13.127s		0	3	0.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	12.081s		0	1	0.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	12.463s		0	5	0.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	12.481s		0	3	0.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	12.511s		0	3	0.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	12.481s		0	3	0.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	13.155s		0	3	0.00
		chip_sw_aes_smoketest	12.874s		0	3	0.00
		chip_sw_aon_timer_smoketest	12.923s		0	3	0.00
		chip_sw_clkmgr_smoketest	13.471s		0	3	0.00
		chip_sw_csrng_smoketest	13.016s		0	3	0.00
		chip_sw_entropy_src_smoketest	13.062s		0	3	0.00
		chip_sw_gpio_smoketest	13.108s		0	3	0.00
		chip_sw_hmac_smoketest	13.154s		0	3	0.00
		chip_sw_kmac_smoketest	13.201s		0	3	0.00
		chip_sw_acc_smoketest	12.144s		0	3	0.00
		chip_sw_pwrmgr_smoketest	12.431s		0	3	0.00
		chip_sw_pwrmgr_usbdev_smoketest	12.425s		0	3	0.00
		chip_sw_rv_plic_smoketest	12.473s		0	3	0.00
		chip_sw_rv_timer_smoketest	12.511s		0	3	0.00
		chip_sw_rstmgr_smoketest	12.359s		0	3	0.00
		chip_sw_sram_ctrl_smoketest	12.473s		0	3	0.00
		chip_sw_uart_smoketest	12.413s		0	3	0.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	12.381s		0	3	0.00
V2	chip_sw_rom_functests	rom_keymgr_functest	12.143s		0	3	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	12.231s		0	3	0.00
V2	chip_sw_secure_boot	rom_e2e_smoke	12.169s		0	3	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	12.563s		0	3	0.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	13.207s		0	3	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	13.255s		0	3	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	12.322s		0	3	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	12.279s		0	3	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	2.870s		0	30	0.00
V2	tl_d_illegal_access	chip_tl_errors	2.870s		0	30	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	5.250s		0	3	0.00
		chip_same_csr_outstanding	6.010s		0	3	0.00
		chip_csr_hw_reset			0	0	--
		chip_csr_rw			0	0	--
V2	tl_d_partial_access	chip_csr_aliasing	5.250s		0	3	0.00
		chip_same_csr_outstanding	6.010s		0	3	0.00
		chip_csr_hw_reset			0	0	--
		chip_csr_rw			0	0	--
V2	xbar_base_random_sequence	xbar_random	1.225m	2.705ms	100	100	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	6.330s	56.838us	100	100	100.00
		xbar_smoke_large_delays	1.438m	10.187ms	100	100	100.00
		xbar_smoke_slow_rsp	1.244m	6.237ms	100	100	100.00
		xbar_random_zero_delays	50.750s	617.015us	100	100	100.00
		xbar_random_large_delays	6.434m	57.253ms	100	100	100.00
		xbar_random_slow_rsp	6.215m	33.819ms	100	100	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	52.270s	1.268ms	100	100	100.00
		xbar_error_and_unmapped_addr	46.540s	1.182ms	100	100	100.00
V2	xbar_error_cases	xbar_error_random	1.467m	2.357ms	100	100	100.00
		xbar_error_and_unmapped_addr	46.540s	1.182ms	100	100	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	2.471m	3.951ms	100	100	100.00
		xbar_access_same_device_slow_rsp	16.473m	94.358ms	100	100	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.230m	2.673ms	100	100	100.00
V2	xbar_stress_all	xbar_stress_all	9.655m	22.060ms	100	100	100.00
		xbar_stress_all_with_error	8.002m	19.769ms	100	100	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	16.212m	13.463ms	100	100	100.00
		xbar_stress_all_with_reset_error	10.785m	9.817ms	100	100	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	12.169s		0	3	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	12.176s		0	3	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	13.161s		0	3	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	13.150s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	12.033s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	12.082s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	12.199s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	12.147s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	12.213s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	12.161s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	12.218s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	12.223s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	13.225s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	12.150s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	12.160s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	12.208s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	12.164s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	12.221s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	12.117s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	12.168s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	13.234s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	12.130s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	12.184s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	12.233s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	12.191s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	12.240s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	12.241s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	12.179s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	12.247s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	12.170s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	12.221s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	12.218s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	12.354s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	12.240s		0	3	0.00
		rom_e2e_asm_init_dev	13.366s		0	3	0.00
		rom_e2e_asm_init_prod	12.340s		0	3	0.00
		rom_e2e_asm_init_prod_end	12.301s		0	3	0.00
		rom_e2e_asm_init_rma	13.192s		0	3	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	12.517s		0	3	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	12.348s		0	3	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	12.511s		0	3	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	12.467s		0	3	0.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	12.410s		0	3	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	12.410s		0	3	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	12.344s		0	3	0.00
		chip_sw_aes_enc_jitter_en	12.396s		0	3	0.00
V2	chip_sw_aes_multi_block	chip_sw_aes_multi_block			0	0	--
V2	chip_sw_aes_interrupt_encryption	chip_sw_aes_interrupt_encryption			0	0	--
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	12.688s		0	3	0.00
V2	chip_sw_aes_prng_reseed	chip_sw_aes_prng_reseed			0	0	--
V2	chip_sw_aes_force_prng_reseed	chip_sw_aes_force_prng_reseed			0	0	--
V2	chip_sw_aes_idle	chip_sw_aes_idle	12.682s		0	3	0.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	12.232s		0	3	0.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	12.394s		0	3	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	12.305s		0	3	0.00
V2	chip_sw_alert_handler_escalation_nmi_reset	chip_sw_alert_handler_escalation_nmi_reset			0	0	--
V2	chip_sw_alert_handler_escalation_methods	chip_sw_alert_handler_escalation_methods			0	0	--
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	13.280s		0	100	0.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	13.297s		0	3	0.00
		chip_plic_all_irqs_10	12.532s		0	3	0.00
		chip_plic_all_irqs_20	12.182s		0	3	0.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	12.396s		0	3	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	12.485s		0	3	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	12.396s		0	3	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	13.389s		0	90	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	12.681s		0	3	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	12.334s		0	3	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	13.433s		0	3	0.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	12.671s		0	3	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	12.669s		0	3	0.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	12.069s		0	3	0.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	12.431s		0	3	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	12.069s		0	3	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	13.341s		0	3	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	13.341s		0	3	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	12.170s		0	5	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	12.206s		0	3	0.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_acc_randomness	12.255s		0	3	0.00
		chip_sw_aes_idle	12.682s		0	3	0.00
		chip_sw_hmac_enc_idle	12.951s		0	3	0.00
		chip_sw_kmac_idle	12.334s		0	3	0.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	12.287s		0	3	0.00
		chip_sw_clkmgr_off_hmac_trans	12.150s		0	3	0.00
		chip_sw_clkmgr_off_kmac_trans	13.096s		0	3	0.00
		chip_sw_clkmgr_off_acc_trans	12.209s		0	3	0.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	13.056s		0	3	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.384s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.433s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.481s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.529s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.384s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	12.432s		0	3	0.00
		chip_sw_ast_clk_outputs	12.314s		0	3	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	12.334s		0	3	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.481s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.529s		0	3	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	12.269s		0	3	0.00
		chip_sw_flash_ctrl_access_jitter_en	12.366s		0	3	0.00
		chip_sw_acc_ecdsa_op_irq_jitter_en	12.253s		0	3	0.00
		chip_sw_aes_enc_jitter_en	12.396s		0	3	0.00
		chip_sw_edn_entropy_reqs_jitter	12.317s		0	3	0.00
		chip_sw_hmac_enc_jitter_en	12.923s		0	3	0.00
		chip_sw_keymgr_key_derivation_jitter_en	12.388s		0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en	12.352s		0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.861s		0	3	0.00
		chip_sw_clkmgr_jitter	13.127s		0	3	0.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	13.132s		0	3	0.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	12.100s		0	3	0.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	12.150s		0	3	0.00
		chip_sw_acc_ecdsa_op_irq_jitter_en_reduced_freq	12.132s		0	3	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	12.324s		0	3	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	13.135s		0	3	0.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	13.400s		0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	12.319s		0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	12.274s		0	3	0.00
		chip_sw_flash_init_reduced_freq	13.147s		0	3	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	13.159s		0	3	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	12.314s		0	3	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	12.300s		0	3	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	12.477s		0	3	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	13.280s		0	100	0.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	12.334s		0	3	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	12.370s		0	3	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	12.279s		0	3	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	12.670s		0	3	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	12.741s		0	3	0.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	12.706s		0	10	0.00
		chip_sw_entropy_src_ast_rng_req	12.321s		0	3	0.00
		chip_sw_edn_entropy_reqs	12.266s		0	3	0.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	12.321s		0	3	0.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	12.370s		0	3	0.00
V2	chip_sw_entropy_src_fuse_en_fw_read	chip_sw_entropy_src_fuse_en_fw_read_test			0	0	--
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	12.233s		0	3	0.00
V2	chip_sw_entropy_src_fw_observe_many_contiguous	chip_sw_entropy_src_fw_observe_many_contiguous			0	0	--
V2	chip_sw_entropy_src_fw_extract_and_insert	chip_sw_entropy_src_fw_extract_and_insert			0	0	--
V2	chip_sw_flash_init	chip_sw_flash_init	13.460s		0	3	0.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	12.388s		0	3	0.00
		chip_sw_flash_ctrl_access_jitter_en	12.366s		0	3	0.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	12.353s		0	3	0.00
		chip_sw_flash_ctrl_ops_jitter_en	12.269s		0	3	0.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	12.150s		0	3	0.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	13.460s		0	3	0.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	12.380s		0	3	0.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	11.965s		0	3	0.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	13.443s		0	3	0.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	12.150s		0	3	0.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	13.443s		0	3	0.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	13.443s		0	3	0.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	13.443s		0	3	0.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	13.443s		0	3	0.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	13.280s		0	100	0.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	6.751m	11.596ms	3	3	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	12.384s		0	3	0.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	12.068s		0	3	0.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	12.068s		0	3	0.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	12.885s		0	3	0.00
		chip_sw_hmac_enc_jitter_en	12.923s		0	3	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	12.951s		0	3	0.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	12.971s		0	3	0.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	12.337s		0	3	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	12.359s		0	3	0.00
		chip_sw_i2c_host_tx_rx_idx1	12.297s		0	3	0.00
		chip_sw_i2c_host_tx_rx_idx2	12.228s		0	3	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	12.332s		0	3	0.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	11.965s		0	3	0.00
		chip_sw_keymgr_key_derivation_jitter_en	12.388s		0	3	0.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	12.184s		0	3	0.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	12.232s		0	3	0.00
V2	chip_sw_keymgr_sideload_acc	chip_sw_keymgr_sideload_acc	12.279s		0	3	0.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	12.313s		0	3	0.00
		chip_sw_kmac_mode_kmac	12.350s		0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en	12.352s		0	3	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	11.965s		0	3	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	13.427s		0	15	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	13.305s		0	3	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	12.403s		0	3	0.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	12.334s		0	3	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	12.305s		0	3	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	12.293s		0	5	0.00
		chip_tap_straps_rma	12.342s		0	5	0.00
		chip_tap_straps_prod	12.367s		0	5	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	12.409s		0	3	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	13.427s		0	15	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	13.427s		0	15	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	13.427s		0	15	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	12.380s		0	3	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	13.443s		0	3	0.00
		chip_sw_flash_rma_unlocked	12.150s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	12.341s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_dev	12.417s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_prod	12.359s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_rma	12.407s		0	3	0.00
		chip_sw_lc_ctrl_transition	13.427s		0	15	0.00
		chip_sw_keymgr_key_derivation	11.965s		0	3	0.00
		chip_sw_rom_ctrl_integrity_check	12.386s		0	3	0.00
		chip_sw_sram_ctrl_execution_main	12.315s		0	3	0.00
		chip_prim_tl_access	6.751m	11.596ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	12.334s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.384s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.433s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.481s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.529s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.384s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	12.432s		0	3	0.00
		chip_tap_straps_dev	12.293s		0	5	0.00
		chip_tap_straps_rma	12.342s		0	5	0.00
		chip_tap_straps_prod	12.367s		0	5	0.00
		chip_rv_dm_lc_disabled	6.245m	11.550ms	1	3	33.33
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	11.449s		0	1	0.00
		chip_sw_lc_ctrl_raw_to_scrap	11.439s		0	1	0.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	11.457s		0	1	0.00
		chip_sw_lc_ctrl_rand_to_scrap	12.336s		0	3	0.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	12.551s		0	3	0.00
		chip_rv_dm_lc_disabled	6.245m	11.550ms	1	3	33.33
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	12.581s		0	3	0.00
		chip_sw_lc_walkthrough_prod	12.436s		0	3	0.00
		chip_sw_lc_walkthrough_prodend	12.484s		0	3	0.00
		chip_sw_lc_walkthrough_rma	12.557s		0	3	0.00
		chip_sw_lc_walkthrough_testunlocks	12.551s		0	3	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	12.458s		0	3	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	12.508s		0	3	0.00
		rom_volatile_raw_unlock	12.340s		0	3	0.00
V2	chip_sw_acc_isa	chip_sw_acc_isa			0	0	--
V2	chip_sw_acc_op	chip_sw_acc_ecdsa_op_irq	12.203s		0	3	0.00
		chip_sw_acc_ecdsa_op_irq_jitter_en	12.253s		0	3	0.00
V2	chip_sw_acc_rnd_entropy	chip_sw_acc_randomness	12.255s		0	3	0.00
V2	chip_sw_acc_urnd_entropy	chip_sw_acc_randomness	12.255s		0	3	0.00
V2	chip_sw_acc_idle	chip_sw_acc_randomness	12.255s		0	3	0.00
V2	chip_sw_acc_mem_scramble	chip_sw_acc_mem_scramble	12.302s		0	3	0.00
V2	chip_sw_acc_keymgr	chip_sw_acc_keymgr			0	0	--
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	13.427s		0	15	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	13.460s		0	3	0.00
		chip_sw_acc_mem_scramble	12.302s		0	3	0.00
		chip_sw_keymgr_key_derivation	11.965s		0	3	0.00
		chip_sw_sram_ctrl_scrambled_access	12.245s		0	3	0.00
		chip_sw_rv_core_ibex_icache_invalidate	12.328s		0	3	0.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	13.460s		0	3	0.00
		chip_sw_acc_mem_scramble	12.302s		0	3	0.00
		chip_sw_keymgr_key_derivation	11.965s		0	3	0.00
		chip_sw_sram_ctrl_scrambled_access	12.245s		0	3	0.00
		chip_sw_rv_core_ibex_icache_invalidate	12.328s		0	3	0.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	13.427s		0	15	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	12.361s		0	3	0.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	12.409s		0	3	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	12.341s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_dev	12.417s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_prod	12.359s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_rma	12.407s		0	3	0.00
		chip_sw_lc_ctrl_transition	13.427s		0	15	0.00
		chip_prim_tl_access	6.751m	11.596ms	3	3	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	6.751m	11.596ms	3	3	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	12.401s		0	1	0.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	12.245s		0	3	0.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	12.315s		0	3	0.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	12.408s		0	3	0.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	12.531s		0	3	0.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	12.507s		0	3	0.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	12.414s		0	3	0.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	12.546s		0	3	0.00
		chip_sw_aon_timer_wdog_bite_reset	13.341s		0	3	0.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	12.480s		0	3	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	12.160s		0	3	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	12.245s		0	3	0.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	12.518s		0	3	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	12.601s		0	3	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	12.458s		0	3	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	12.558s		0	3	0.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	12.522s		0	3	0.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	12.303s		0	3	0.00
		chip_sw_pwrmgr_all_reset_reqs	12.338s		0	3	0.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	12.532s		0	3	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	12.455s		0	3	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	13.280s		0	100	0.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	12.386s		0	3	0.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	12.386s		0	3	0.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	12.338s		0	3	0.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	12.522s		0	3	0.00
		chip_sw_pwrmgr_wdog_reset	12.160s		0	3	0.00
		chip_sw_pwrmgr_smoketest	12.431s		0	3	0.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	12.050s		0	3	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	12.504s		0	3	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	12.513s		0	3	0.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	12.485s		0	3	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	12.511s		0	3	0.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	13.280s		0	100	0.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	13.433s		0	3	0.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	12.680s		0	3	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	12.669s		0	3	0.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	12.129s		0	3	0.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	12.328s		0	3	0.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	12.504s		0	3	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	12.504s		0	3	0.00
V2	chip_sw_rv_core_ibex_smoke	chip_sw_rv_core_ibex_smoke			0	0	--
V2	chip_sw_rv_core_ibex_epmp_smoke	chip_sw_rv_core_ibex_epmp_smoke			0	0	--
V2	chip_sw_rv_core_ibex_mem_smoke	chip_sw_rv_core_ibex_mem_smoke			0	0	--
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	22.796m	17.587ms	3	3	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	13.568m	13.345ms	3	3	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	12.050s		0	3	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	12.014s		0	3	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	12.361s		0	3	0.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	12.342s		0	5	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	6.245m	11.550ms	1	3	33.33
V2	chip_rv_dm_jtag	chip_rv_dm_jtag			0	0	--
V2	chip_rv_dm_dtm	chip_rv_dm_dtm			0	0	--
V2	chip_rv_dm_control_status	chip_rv_dm_control_status			0	0	--
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	13.297s		0	3	0.00
		chip_plic_all_irqs_10	12.532s		0	3	0.00
		chip_plic_all_irqs_20	12.182s		0	3	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	12.235s		0	3	0.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	12.616s		0	3	0.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	12.169s		0	3	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	12.346s		0	3	0.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	12.358s		0	3	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	12.354s		0	3	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	12.342s		0	3	0.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	12.245s		0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.861s		0	3	0.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	12.942s		0	3	0.00
		chip_sw_sleep_sram_ret_contents_scramble	12.414s		0	3	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	12.315s		0	3	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	13.280s		0	100	0.00
		chip_sw_data_integrity_escalation	13.196s		0	6	0.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	12.303s		0	3	0.00
		chip_sw_sysrst_ctrl_reset	12.568s		0	3	0.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	12.525s		0	3	0.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	12.592s		0	3	0.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	12.282s		0	3	0.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	12.568s		0	3	0.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	12.568s		0	3	0.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	12.616s		0	3	0.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	12.616s		0	3	0.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	12.544s		0	3	0.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	12.410s		0	3	0.00
V2	chip_sw_usbdev_mem	chip_sw_usbdev_mem			0	0	--
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	11.180s		0	1	0.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	11.186s		0	1	0.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	11.189s		0	1	0.00
V2	chip_sw_usbdev_sof	chip_sw_usbdev_sof			0	0	--
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	12.232s		0	1	0.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	12.273s		0	1	0.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	11.211s		0	1	0.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	11.184s		0	1	0.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	11.219s		0	1	0.00
V2		TOTAL			1720	2640	65.15
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	12.335s		0	3	0.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	12.059s		0	3	0.00
V2S		TOTAL			0	6	0.00
V3	chip_sw_usb_suspend	chip_sw_usb_suspend			0	0	--
V3	chip_sw_coremark	chip_sw_coremark	12.951s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	13.292s		0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	13.361s		0	1	0.00
		rom_e2e_jtag_debug_dev	12.291s		0	1	0.00
		rom_e2e_jtag_debug_rma	12.184s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	12.232s		0	1	0.00
		rom_e2e_jtag_inject_dev	12.281s		0	1	0.00
		rom_e2e_jtag_inject_rma	12.330s		0	1	0.00
V3	rom_bootstrap_rma	rom_bootstrap_rma			0	0	--
V3	rom_e2e_weak_straps	rom_e2e_weak_straps			0	0	--
V3	rom_e2e_self_hash	rom_e2e_self_hash	12.309s		0	3	0.00
V3	manuf_cp_unlock_raw	manuf_cp_unlock_raw			0	0	--
V3	manuf_scrap	manuf_scrap			0	0	--
V3	manuf_cp_yield_test	manuf_cp_yield_test			0	0	--
V3	manuf_cp_ast_test_execution	manuf_cp_ast_test_execution			0	0	--
V3	manuf_cp_device_info_flash_wr	manuf_cp_device_info_flash_wr			0	0	--
V3	manuf_cp_test_lock	manuf_cp_test_lock			0	0	--
V3	manuf_ft_exit_token	manuf_ft_exit_token			0	0	--
V3	manuf_ft_sku_individualization_preop	manuf_ft_sku_individualization_preop			0	0	--
V3	manuf_ft_sku_individualization	manuf_ft_sku_individualization			0	0	--
V3	manuf_ft_provision_rma_token_and_personalization	manuf_ft_provision_rma_token_and_personalization			0	0	--
V3	manuf_ft_load_transport_image	manuf_ft_load_transport_image			0	0	--
V3	manuf_ft_load_certificates	manuf_ft_load_certificates			0	0	--
V3	manuf_ft_eom	manuf_ft_eom			0	0	--
V3	manuf_rma_entry	manuf_rma_entry			0	0	--
V3	manuf_sram_program_crc_functest	manuf_sram_program_crc_functest			0	0	--
V3	chip_sw_adc_ctrl_normal	chip_sw_adc_ctrl_normal			0	0	--
V3	chip_sw_adc_ctrl_oneshot	chip_sw_adc_ctrl_oneshot			0	0	--
V3	chip_sw_aes_stall_test	chip_sw_aes_stall_test			0	0	--
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	13.179s		0	3	0.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	12.400s		0	3	0.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	12.349s		0	3	0.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	12.632s		0	3	0.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	12.449s		0	3	0.00
V3	chip_sw_entropy_src_bypass_mode_health_tests	chip_sw_entropy_src_bypass_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_fips_mode_health_tests	chip_sw_entropy_src_fips_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_validation	chip_sw_entropy_src_validation			0	0	--
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	13.343s		0	3	0.00
V3	chip_sw_hmac_sha2_stress	chip_sw_hmac_sha2_stress			0	0	--
V3	chip_sw_hmac_stress	chip_sw_hmac_stress			0	0	--
V3	chip_sw_hmac_endianness	chip_sw_hmac_endianness			0	0	--
V3	chip_sw_hmac_secure_wipe	chip_sw_hmac_secure_wipe			0	0	--
V3	chip_sw_hmac_error_conditions	chip_sw_hmac_error_conditions			0	0	--
V3	chip_sw_i2c_speed	chip_sw_i2c_speed			0	0	--
V3	chip_sw_i2c_override	chip_sw_i2c_override			0	0	--
V3	chip_sw_i2c_clockstretching	chip_sw_i2c_clockstretching			0	0	--
V3	chip_sw_i2c_nack	chip_sw_i2c_nack			0	0	--
V3	chip_sw_i2c_repeatedstart	chip_sw_i2c_repeatedstart			0	0	--
V3	chip_sw_keymgr_sideload_kmac_error	chip_sw_keymgr_sideload_kmac_error			0	0	--
V3	chip_sw_keymgr_derive_attestation	chip_sw_keymgr_derive_attestation			0	0	--
V3	chip_sw_keymgr_derive_sealing	chip_sw_keymgr_derive_sealing			0	0	--
V3	chip_sw_kmac_sha3_stress	chip_sw_kmac_sha3_stress			0	0	--
V3	chip_sw_kmac_shake_stress	chip_sw_kmac_shake_stress			0	0	--
V3	chip_sw_kmac_cshake_stress	chip_sw_kmac_cshake_stress			0	0	--
V3	chip_sw_kmac_kmac_stress	chip_sw_kmac_kmac_stress			0	0	--
V3	chip_sw_kmac_kmac_key_sideload	chip_sw_kmac_kmac_key_sideload			0	0	--
V3	chip_sw_kmac_endianness	chip_sw_kmac_endianness			0	0	--
V3	chip_sw_kmac_entropy_stress	chip_sw_kmac_entropy_stress			0	0	--
V3	chip_sw_kmac_error_conditions	chip_sw_kmac_error_conditions			0	0	--
V3	chip_sw_lc_ctrl_kmac_error	chip_sw_lc_ctrl_kmac_error			0	0	--
V3	chip_sw_lc_ctrl_debug_access	chip_sw_lc_ctrl_debug_access			0	0	--
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	12.416s		0	3	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	12.381s		0	1	0.00
V3	otp_ctrl_calibration	otp_ctrl_calibration			0	0	--
V3	otp_ctrl_partition_access_locked	otp_ctrl_partition_access_locked			0	0	--
V3	otp_ctrl_check_timeout	otp_ctrl_check_timeout			0	0	--
V3	chip_sw_pwm_smoketest	chip_sw_pwm_smoketest			0	0	--
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	13.120s		0	3	0.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	12.207s		0	3	0.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	12.338s		0	3	0.00
V3	chip_sw_rom_ctrl_kmac_error	chip_sw_rom_ctrl_kmac_error			0	0	--
V3	chip_sw_rom_ctrl_digests	chip_sw_rom_ctrl_digests			0	0	--
V3	chip_sw_rv_core_ibex_alerts	chip_sw_rv_core_ibex_alerts			0	0	--
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	13.361s		0	1	0.00
		rom_e2e_jtag_debug_dev	12.291s		0	1	0.00
		rom_e2e_jtag_debug_rma	12.184s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	12.104s		0	3	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	13.280s		0	100	0.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	12.302s		0	3	0.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	12.302s		0	3	0.00
V3	chip_sw_spi_device_pass_through_flash_model	chip_sw_spi_device_pass_through_flash_model			0	0	--
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	12.295s		0	3	0.00
V3	chip_sw_spi_host_pass_through	chip_sw_spi_host_pass_through			0	0	--
V3	chip_sw_spi_host_configuration	chip_sw_spi_host_configuration			0	0	--
V3	chip_sw_spi_host_events	chip_sw_spi_host_events			0	0	--
V3	chip_sw_sram_memset	chip_sw_sram_memset			0	0	--
V3	chip_sw_sram_readback	chip_sw_sram_readback			0	0	--
V3	chip_sw_sram_subword_access	chip_sw_sram_subword_access			0	0	--
V3	chip_sw_uart_parity	chip_sw_uart_parity			0	0	--
V3	chip_sw_uart_line_loopback	chip_sw_uart_line_loopback			0	0	--
V3	chip_sw_uart_system_loopback	chip_sw_uart_system_loopback			0	0	--
V3	chip_sw_uart_line_break	chip_sw_uart_line_break			0	0	--
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	12.403s		0	5	0.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	12.277s		0	1	0.00
V3	chip_sw_usbdev_iso	chip_sw_usbdev_iso			0	0	--
V3	chip_sw_usbdev_mixed	chip_sw_usbdev_mixed			0	0	--
V3	chip_sw_usbdev_suspend_resume	chip_sw_usbdev_suspend_resume			0	0	--
V3	chip_sw_usbdev_aon_wake_reset	chip_sw_usbdev_aon_wake_reset			0	0	--
V3	chip_sw_usbdev_aon_wake_disconnect	chip_sw_usbdev_aon_wake_disconnect			0	0	--
V3		TOTAL			0	51	0.00
	Unmapped tests	chip_sival_flash_info_access	12.343s		0	3	0.00
		chip_sw_rstmgr_rst_cnsty_escalation	12.839s		0	3	0.00
		chip_sw_otp_ctrl_rot_auth_config	12.416s		0	1	0.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	12.471s		0	3	0.00
		chip_sw_otp_ctrl_descrambling	12.522s		0	3	0.00
		chip_sw_pwrmgr_lowpower_cancel	12.364s		0	3	0.00
		chip_sw_pwrmgr_sleep_wake_5_bug	13.040s		0	3	0.00
		chip_sw_flash_ctrl_write_clear	12.376s		0	3	0.00
		chip_egret_csr_hw_reset	2.530s		0	5	0.00
		chip_egret_csr_rw	2.810s		0	20	0.00
		chip_egret_csr_bit_bash	2.440s		0	5	0.00
		chip_egret_csr_aliasing	2.580s		0	5	0.00
		chip_egret_same_csr_outstanding	2.800s		0	20	0.00
		chip_egret_csr_mem_rw_with_rand_reset	2.760s		0	20	0.00
		TOTAL			1820	2965	61.38

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	21	14	0	0.00
V1	18	15	1	5.56
V2	294	275	21	7.14
V2S	2	2	0	0.00
V3	93	23	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
65.73	72.37	68.84	57.92	28.57	70.46	65.33	96.63

Failure Buckets

Job returned non-zero exit code has 1029 failures:

Test chip_sw_example_flash has 3 failures.

0.chip_sw_example_flash.64458397802728597641568919326537715747397199839532221892283264168323737029936
Log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_sw_example_flash/latest/run.log

  pid=2746172
  owner=client
  cwd=/home/runner/_work/pavona/pavona
  
  Waiting for it to complete...
  Another command (pid=2746172) is running. Waiting for it to complete on the server (server_pid=2746178)...
  ERROR: Error while parsing 'release 8.10 (Cerulean Leopard) //sw/device/tests:example_test_from_flash_sim_dv': unexpected token '8.10' after query expression 'release'
  
  _run_cmd -> had a non-zero return code of 2.
  make: *** [/home/runner/_work/pavona/pavona/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1

1.chip_sw_example_flash.100442690000618961567624589319207539339131600073168568184567552295111734063065
Log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/1.chip_sw_example_flash/latest/run.log

    cquery_common_opts=['--ui_event_filters=-info', '--noshow_progress']
  
  INFO: [build_sw_collateral_for_sim.py:202] cquery_cmd = ./bazelisk.sh cquery //sw/device/tests:example_test_from_flash_sim_dv --ui_event_filters=-info --noshow_progress --output=label_kind
  ---- STDOUT ----
  
  ---- STDERR ----
  ERROR: Error while parsing 'release 8.10 (Cerulean Leopard) //sw/device/tests:example_test_from_flash_sim_dv': unexpected token '8.10' after query expression 'release'
  
  _run_cmd -> had a non-zero return code of 2.
  make: *** [/home/runner/_work/pavona/pavona/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1

... and 1 more failures.

Test chip_sw_example_rom has 3 failures.

0.chip_sw_example_rom.47955689283548161956909880452377493569571339191505584529305316381294265530411
Log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_sw_example_rom/latest/run.log

  
  INFO: [build_sw_collateral_for_sim.py:202] cquery_cmd = ./bazelisk.sh cquery //sw/device/tests:example_test_from_rom_sim_dv --ui_event_filters=-info --noshow_progress --output=label_kind
  ---- STDOUT ----
  
  ---- STDERR ----
  Starting local Bazel server (8.0.1) and connecting to it...
  ERROR: Error while parsing 'release 8.10 (Cerulean Leopard) //sw/device/tests:example_test_from_rom_sim_dv': unexpected token '8.10' after query expression 'release'
  
  _run_cmd -> had a non-zero return code of 2.
  make: *** [/home/runner/_work/pavona/pavona/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1

1.chip_sw_example_rom.80056760953139281528799911509629973362610258813701557132764620807641785070412
Log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/1.chip_sw_example_rom/latest/run.log

    cquery_common_opts=['--ui_event_filters=-info', '--noshow_progress']
  
  INFO: [build_sw_collateral_for_sim.py:202] cquery_cmd = ./bazelisk.sh cquery //sw/device/tests:example_test_from_rom_sim_dv --ui_event_filters=-info --noshow_progress --output=label_kind
  ---- STDOUT ----
  
  ---- STDERR ----
  ERROR: Error while parsing 'release 8.10 (Cerulean Leopard) //sw/device/tests:example_test_from_rom_sim_dv': unexpected token '8.10' after query expression 'release'
  
  _run_cmd -> had a non-zero return code of 2.
  make: *** [/home/runner/_work/pavona/pavona/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1

... and 1 more failures.

Test chip_sw_example_manufacturer has 3 failures.

0.chip_sw_example_manufacturer.1260651726665076199035104708268188526442551833926472254666392640629657066196
Log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  pid=2746172
  owner=client
  cwd=/home/runner/_work/pavona/pavona
  
  Waiting for it to complete...
  Another command (pid=2746172) is running. Waiting for it to complete on the server (server_pid=2746178)...
  ERROR: Error while parsing 'release 8.10 (Cerulean Leopard) @manufacturer_test_hooks//:example_test_sim_dv': unexpected token '8.10' after query expression 'release'
  
  _run_cmd -> had a non-zero return code of 2.
  make: *** [/home/runner/_work/pavona/pavona/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1

1.chip_sw_example_manufacturer.58574997149727350704903313558141847373156119967650244643809833831351327839072
Log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/1.chip_sw_example_manufacturer/latest/run.log

    cquery_common_opts=['--ui_event_filters=-info', '--noshow_progress']
  
  INFO: [build_sw_collateral_for_sim.py:202] cquery_cmd = ./bazelisk.sh cquery @manufacturer_test_hooks//:example_test_sim_dv --ui_event_filters=-info --noshow_progress --output=label_kind
  ---- STDOUT ----
  
  ---- STDERR ----
  ERROR: Error while parsing 'release 8.10 (Cerulean Leopard) @manufacturer_test_hooks//:example_test_sim_dv': unexpected token '8.10' after query expression 'release'
  
  _run_cmd -> had a non-zero return code of 2.
  make: *** [/home/runner/_work/pavona/pavona/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1

... and 1 more failures.

Test chip_sw_example_concurrency has 3 failures.

0.chip_sw_example_concurrency.103726215355628661625891978412035144894923854378372577468553455514390875709303
Log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_sw_example_concurrency/latest/run.log

  
  INFO: [build_sw_collateral_for_sim.py:202] cquery_cmd = ./bazelisk.sh cquery //sw/device/tests:example_concurrency_test_sim_dv --ui_event_filters=-info --noshow_progress --output=label_kind
  ---- STDOUT ----
  
  ---- STDERR ----
  Another command (pid=2746172) is running. Waiting for it to complete on the server (server_pid=2746178)...
  ERROR: Error while parsing 'release 8.10 (Cerulean Leopard) //sw/device/tests:example_concurrency_test_sim_dv': unexpected token '8.10' after query expression 'release'
  
  _run_cmd -> had a non-zero return code of 2.
  make: *** [/home/runner/_work/pavona/pavona/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1

1.chip_sw_example_concurrency.73200979548256482620137074615562725175061747025621016093550951190189025722222
Log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/1.chip_sw_example_concurrency/latest/run.log

    cquery_common_opts=['--ui_event_filters=-info', '--noshow_progress']
  
  INFO: [build_sw_collateral_for_sim.py:202] cquery_cmd = ./bazelisk.sh cquery //sw/device/tests:example_concurrency_test_sim_dv --ui_event_filters=-info --noshow_progress --output=label_kind
  ---- STDOUT ----
  
  ---- STDERR ----
  ERROR: Error while parsing 'release 8.10 (Cerulean Leopard) //sw/device/tests:example_concurrency_test_sim_dv': unexpected token '8.10' after query expression 'release'
  
  _run_cmd -> had a non-zero return code of 2.
  make: *** [/home/runner/_work/pavona/pavona/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1

... and 1 more failures.

Test chip_sival_flash_info_access has 3 failures.

0.chip_sival_flash_info_access.61467169882838328419439216349107910885225282355715638503691677272167177657818
Log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_sival_flash_info_access/latest/run.log

  
  INFO: [build_sw_collateral_for_sim.py:202] cquery_cmd = ./bazelisk.sh cquery //sw/device/tests:flash_ctrl_info_access_lc_sim_dv --ui_event_filters=-info --noshow_progress --output=label_kind
  ---- STDOUT ----
  
  ---- STDERR ----
  Another command (pid=2746172) is running. Waiting for it to complete on the server (server_pid=2746178)...
  ERROR: Error while parsing 'release 8.10 (Cerulean Leopard) //sw/device/tests:flash_ctrl_info_access_lc_sim_dv': unexpected token '8.10' after query expression 'release'
  
  _run_cmd -> had a non-zero return code of 2.
  make: *** [/home/runner/_work/pavona/pavona/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1

1.chip_sival_flash_info_access.94488206031416195262695772603378953538741411872814066490670639754664636712235
Log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/1.chip_sival_flash_info_access/latest/run.log

    cquery_common_opts=['--ui_event_filters=-info', '--noshow_progress']
  
  INFO: [build_sw_collateral_for_sim.py:202] cquery_cmd = ./bazelisk.sh cquery //sw/device/tests:flash_ctrl_info_access_lc_sim_dv --ui_event_filters=-info --noshow_progress --output=label_kind
  ---- STDOUT ----
  
  ---- STDERR ----
  ERROR: Error while parsing 'release 8.10 (Cerulean Leopard) //sw/device/tests:flash_ctrl_info_access_lc_sim_dv': unexpected token '8.10' after query expression 'release'
  
  _run_cmd -> had a non-zero return code of 2.
  make: *** [/home/runner/_work/pavona/pavona/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1

... and 1 more failures.

... and 291 more tests.

UVM_WARNING @ * us: [BDTYP] Cannot create an object of type 'chip_egret_common_vseq' because it is not registered with the factory.

has 105 failures:

Test chip_tl_errors has 30 failures.

0.chip_tl_errors.31685071101271615104611703816437594981482848767804650591535474906453147117854
Line 196, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_WARNING @   0.000000 us: [BDTYP] Cannot create an object of type 'chip_egret_common_vseq' because it is not registered with the factory.
  UVM_INFO @   0.000000 us: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
  #### Factory Configuration (*)
  
  No instance overrides are registered with this factory

1.chip_tl_errors.91345156895114845306323979810433770089332550185696044878151821707858883893479
Line 196, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/1.chip_tl_errors/latest/run.log

  UVM_WARNING @   0.000000 us: [BDTYP] Cannot create an object of type 'chip_egret_common_vseq' because it is not registered with the factory.
  UVM_INFO @   0.000000 us: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
  #### Factory Configuration (*)
  
  No instance overrides are registered with this factory

... and 28 more failures.

Test chip_egret_csr_hw_reset has 5 failures.

0.chip_egret_csr_hw_reset.64054875564783212889172612128407288082118930885612230315834302633690706472177
Line 196, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_egret_csr_hw_reset/latest/run.log

  UVM_WARNING @   0.000000 us: [BDTYP] Cannot create an object of type 'chip_egret_common_vseq' because it is not registered with the factory.
  UVM_INFO @   0.000000 us: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
  #### Factory Configuration (*)
  
  No instance overrides are registered with this factory

1.chip_egret_csr_hw_reset.97047885382822975883362324736689888809489638206994594108789810064861221079049
Line 196, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/1.chip_egret_csr_hw_reset/latest/run.log

  UVM_WARNING @   0.000000 us: [BDTYP] Cannot create an object of type 'chip_egret_common_vseq' because it is not registered with the factory.
  UVM_INFO @   0.000000 us: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
  #### Factory Configuration (*)
  
  No instance overrides are registered with this factory

... and 3 more failures.

Test chip_egret_csr_rw has 20 failures.

0.chip_egret_csr_rw.73479799733829028706522668382113588884705395262168404727463639008418930391
Line 196, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_egret_csr_rw/latest/run.log

  UVM_WARNING @   0.000000 us: [BDTYP] Cannot create an object of type 'chip_egret_common_vseq' because it is not registered with the factory.
  UVM_INFO @   0.000000 us: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
  #### Factory Configuration (*)
  
  No instance overrides are registered with this factory

1.chip_egret_csr_rw.50666020431865905668824137971013233854320427817803989595422017775314360412007
Line 196, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/1.chip_egret_csr_rw/latest/run.log

  UVM_WARNING @   0.000000 us: [BDTYP] Cannot create an object of type 'chip_egret_common_vseq' because it is not registered with the factory.
  UVM_INFO @   0.000000 us: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
  #### Factory Configuration (*)
  
  No instance overrides are registered with this factory

... and 18 more failures.

Test chip_egret_csr_bit_bash has 5 failures.

0.chip_egret_csr_bit_bash.111739681865652473049798730548732805085691342193404831285153826340773810039289
Line 196, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_egret_csr_bit_bash/latest/run.log

  UVM_WARNING @   0.000000 us: [BDTYP] Cannot create an object of type 'chip_egret_common_vseq' because it is not registered with the factory.
  UVM_INFO @   0.000000 us: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
  #### Factory Configuration (*)
  
  No instance overrides are registered with this factory

1.chip_egret_csr_bit_bash.489470767953528572676558941468495513020516193694967428448270430568044560372
Line 196, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/1.chip_egret_csr_bit_bash/latest/run.log

  UVM_WARNING @   0.000000 us: [BDTYP] Cannot create an object of type 'chip_egret_common_vseq' because it is not registered with the factory.
  UVM_INFO @   0.000000 us: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
  #### Factory Configuration (*)
  
  No instance overrides are registered with this factory

... and 3 more failures.

Test chip_egret_csr_aliasing has 5 failures.

0.chip_egret_csr_aliasing.63564676603799631036979059468280694991524879714408376396745378636776485263943
Line 196, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_egret_csr_aliasing/latest/run.log

  UVM_WARNING @   0.000000 us: [BDTYP] Cannot create an object of type 'chip_egret_common_vseq' because it is not registered with the factory.
  UVM_INFO @   0.000000 us: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
  #### Factory Configuration (*)
  
  No instance overrides are registered with this factory

1.chip_egret_csr_aliasing.9659096332259394218956866133118861492187249595841444311579095709927501933743
Line 196, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/1.chip_egret_csr_aliasing/latest/run.log

  UVM_WARNING @   0.000000 us: [BDTYP] Cannot create an object of type 'chip_egret_common_vseq' because it is not registered with the factory.
  UVM_INFO @   0.000000 us: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
  #### Factory Configuration (*)
  
  No instance overrides are registered with this factory

... and 3 more failures.

... and 2 more tests.

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 9 failures:
- Test chip_csr_bit_bash has 3 failures.
  - 0.chip_csr_bit_bash.16027789225831611026346544532532240013882381818978308809947195998172254496257
    Line 120, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_csr_bit_bash.19027413819439640631517785585856933941957099839493514512045962047878021393372
    Line 120, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/1.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test chip_csr_aliasing has 3 failures.
  - 0.chip_csr_aliasing.21821425466403902034822676547244058730515484792797496517098576650909658682077
    Line 120, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_csr_aliasing.74763647425658015919308156709669023928174330636901533083548683189890525831692
    Line 120, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/1.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test chip_same_csr_outstanding has 3 failures.
  - 0.chip_same_csr_outstanding.40808643415915776565062766596695544895669826322629732343860740184434381636695
    Line 120, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_same_csr_outstanding.3134659929346405031456141384262097042892154119873295899143060742511672630513
    Line 120, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/1.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

UVM_ERROR @ * us: (cip_base_vseq.sv:649) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch

has 2 failures:

Test chip_rv_dm_lc_disabled has 2 failures.

0.chip_rv_dm_lc_disabled.18489064626391216559445242376071117109207849779437185053957941956012837927986
Line 221, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log

  UVM_ERROR @ 2519.401497 us: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x106cc read out mismatch
  UVM_INFO @ 2519.401497 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.chip_rv_dm_lc_disabled.49288791781949713186408591354640592955382353632721609821231382575495389935939
Line 278, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/2.chip_rv_dm_lc_disabled/latest/run.log

  UVM_ERROR @ 9599.229000 us: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x1077c read out mismatch
  UVM_INFO @ 9599.229000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---