CLKMGR/DRAGONFLY Simulation Results

Saturday June 06 2026 03:15:30 UTC

GitHub Revision: 285e653a0b

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	2.610s	167.600us	50	50	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	1.040s	24.916us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	1.840s	108.591us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	46.890s	4.297ms	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	2.550s	156.672us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	3.570s	255.977us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	1.840s	108.591us	20	20	100.00
		clkmgr_csr_aliasing	2.550s	156.672us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	peri_enables	clkmgr_peri	2.090s	124.133us	50	50	100.00
V2	trans_enables	clkmgr_trans	2.200s	123.352us	50	50	100.00
V2	clk_status	clkmgr_clk_status	2.110s	192.763us	50	50	100.00
V2	jitter	clkmgr_smoke	2.610s	167.600us	50	50	100.00
V2	frequency	clkmgr_frequency	2.480s	264.117us	50	50	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	1.580s	59.775us	17	50	34.00
V2	frequency_overflow	clkmgr_frequency	2.480s	264.117us	50	50	100.00
V2	stress_all	clkmgr_stress_all	14.370s	1.130ms	22	50	44.00
V2	intr_test	clkmgr_intr_test			0	0	--
V2	alert_test	clkmgr_alert_test	3.420s	408.835us	50	50	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	5.100s	386.841us	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	5.100s	386.841us	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	1.040s	24.916us	5	5	100.00
		clkmgr_csr_rw	1.840s	108.591us	20	20	100.00
		clkmgr_csr_aliasing	2.550s	156.672us	5	5	100.00
		clkmgr_same_csr_outstanding	1.850s	98.801us	20	20	100.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	1.040s	24.916us	5	5	100.00
		clkmgr_csr_rw	1.840s	108.591us	20	20	100.00
		clkmgr_csr_aliasing	2.550s	156.672us	5	5	100.00
		clkmgr_same_csr_outstanding	1.850s	98.801us	20	20	100.00
V2		TOTAL			329	390	84.36
V2S	tl_intg_err	clkmgr_sec_cm	11.110s	1.121ms	5	5	100.00
		clkmgr_tl_intg_err	5.360s	462.342us	20	20	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	2.320s	131.891us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	2.320s	131.891us	20	20	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	2.320s	131.891us	20	20	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	2.320s	131.891us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	3.280s	202.270us	20	20	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	5.360s	462.342us	20	20	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	2.480s	264.117us	50	50	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	1.580s	59.775us	17	50	34.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	2.320s	131.891us	20	20	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	4.630s	359.410us	50	50	100.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	1.840s	108.591us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	11.110s	1.121ms	5	5	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	1.840s	108.591us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	1.840s	108.591us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	11.110s	1.121ms	5	5	100.00
V2S		TOTAL			115	115	100.00
V3	regwen	clkmgr_regwen	3.910s	235.965us	50	50	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	1.693m	13.457ms	8	50	16.00
V3		TOTAL			58	100	58.00
		TOTAL			607	710	85.49

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	10	9	7	70.00
V2S	5	5	5	100.00
V3	2	2	1	50.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.37	98.53	94.51	100.00	100.00	98.23	96.07	87.26

Failure Buckets

• UVM_ERROR (clkmgr_frequency_timeout_vseq.sv:113) [clkmgr_frequency_timeout_vseq] Check failed current_alert_count != prior_alert_count (* [*] vs * [*]) expected some alerts to fire has 71 failures:
  • Test clkmgr_frequency_timeout has 20 failures.

    • 1.clkmgr_frequency_timeout.57886395549520857565839317133082225189761124867080918693530764578316066461623
      Line 84, in log /home/runner/_work/pavona/pavona/scratch/main/clkmgr_top_dragonfly-sim-vcs/1.clkmgr_frequency_timeout/latest/run.log

        UVM_ERROR @   6576208 ps: (clkmgr_frequency_timeout_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Check failed current_alert_count != prior_alert_count (0 [0x0] vs 0 [0x0]) expected some alerts to fire
        UVM_INFO @   6576208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.clkmgr_frequency_timeout.67093626266186036297496908716721372084368707332090307758443739172796869324713
      Line 88, in log /home/runner/_work/pavona/pavona/scratch/main/clkmgr_top_dragonfly-sim-vcs/2.clkmgr_frequency_timeout/latest/run.log

        UVM_ERROR @  14899505 ps: (clkmgr_frequency_timeout_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Check failed current_alert_count != prior_alert_count (2 [0x2] vs 2 [0x2]) expected some alerts to fire
        UVM_INFO @  14899505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 18 more failures.

  • Test clkmgr_stress_all_with_rand_reset has 29 failures.

    • 1.clkmgr_stress_all_with_rand_reset.29973649564883547648196045291613049156116260021048336699369486418456961150830
      Line 95, in log /home/runner/_work/pavona/pavona/scratch/main/clkmgr_top_dragonfly-sim-vcs/1.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  16871531 ps: (clkmgr_frequency_timeout_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Check failed current_alert_count != prior_alert_count (5 [0x5] vs 5 [0x5]) expected some alerts to fire
        UVM_INFO @  16871531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 5.clkmgr_stress_all_with_rand_reset.59249036450394937732902931889897272417089707323659730243626361502404217965046
      Line 87, in log /home/runner/_work/pavona/pavona/scratch/main/clkmgr_top_dragonfly-sim-vcs/5.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @   3853083 ps: (clkmgr_frequency_timeout_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Check failed current_alert_count != prior_alert_count (1 [0x1] vs 1 [0x1]) expected some alerts to fire
        UVM_INFO @   3853083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 27 more failures.

  • Test clkmgr_stress_all has 22 failures.

    • 1.clkmgr_stress_all.88841262305634407835124282975179376827811621265751864621867152224418121742328
      Line 112, in log /home/runner/_work/pavona/pavona/scratch/main/clkmgr_top_dragonfly-sim-vcs/1.clkmgr_stress_all/latest/run.log

        UVM_ERROR @ 188568082 ps: (clkmgr_frequency_timeout_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Check failed current_alert_count != prior_alert_count (42 [0x2a] vs 42 [0x2a]) expected some alerts to fire
        UVM_INFO @ 188568082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.clkmgr_stress_all.4802169269911596220470335720080370594989672304511144547887475669177558463037
      Line 97, in log /home/runner/_work/pavona/pavona/scratch/main/clkmgr_top_dragonfly-sim-vcs/3.clkmgr_stress_all/latest/run.log

        UVM_ERROR @  31860195 ps: (clkmgr_frequency_timeout_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Check failed current_alert_count != prior_alert_count (7 [0x7] vs 7 [0x7]) expected some alerts to fire
        UVM_INFO @  31860195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 20 more failures.

• UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b* has 32 failures:
  • Test clkmgr_frequency_timeout has 13 failures.

    • 0.clkmgr_frequency_timeout.37729765640757663611098795298030900254783255473186610255932924015059673179898
      Line 89, in log /home/runner/_work/pavona/pavona/scratch/main/clkmgr_top_dragonfly-sim-vcs/0.clkmgr_frequency_timeout/latest/run.log

        UVM_ERROR @  22971168 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00
        UVM_INFO @  22971168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.clkmgr_frequency_timeout.94724201116176647680435889655442051273217256938871280855613233034892155092441
      Line 87, in log /home/runner/_work/pavona/pavona/scratch/main/clkmgr_top_dragonfly-sim-vcs/3.clkmgr_frequency_timeout/latest/run.log

        UVM_ERROR @  23346231 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00
        UVM_INFO @  23346231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 11 more failures.

  • Test clkmgr_stress_all_with_rand_reset has 13 failures.

    • 0.clkmgr_stress_all_with_rand_reset.65690312549021268601463699485613249882251774190933168703328145155622419297542
      Line 148, in log /home/runner/_work/pavona/pavona/scratch/main/clkmgr_top_dragonfly-sim-vcs/0.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  51072113 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00
        UVM_INFO @  51072113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.clkmgr_stress_all_with_rand_reset.52782797330785692189678339914802870772427523968436866335611159341198403083641
      Line 92, in log /home/runner/_work/pavona/pavona/scratch/main/clkmgr_top_dragonfly-sim-vcs/3.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  80036944 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00
        UVM_INFO @  80036944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 11 more failures.

  • Test clkmgr_stress_all has 6 failures.

    • 5.clkmgr_stress_all.50113133553965804470391851436935213566774709727009324271155171961806327068192
      Line 113, in log /home/runner/_work/pavona/pavona/scratch/main/clkmgr_top_dragonfly-sim-vcs/5.clkmgr_stress_all/latest/run.log

        UVM_ERROR @ 155737257 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00
        UVM_INFO @ 155737257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 11.clkmgr_stress_all.50505391816121941965907621162417800687706481021462904277936128945840422271834
      Line 104, in log /home/runner/_work/pavona/pavona/scratch/main/clkmgr_top_dragonfly-sim-vcs/11.clkmgr_stress_all/latest/run.log

        UVM_ERROR @ 109823712 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00
        UVM_INFO @ 109823712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 4 more failures.