CLKMGR/EGRET Simulation Results

Saturday June 06 2026 03:15:30 UTC

GitHub Revision: 285e653a0b

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	1.200s	149.079us	50	50	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	0.910s	39.589us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	0.990s	80.983us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	6.970s	920.613us	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	2.230s	367.955us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	1.890s	279.603us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	0.990s	80.983us	20	20	100.00
		clkmgr_csr_aliasing	2.230s	367.955us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	peri_enables	clkmgr_peri	1.140s	210.269us	50	50	100.00
V2	trans_enables	clkmgr_trans	1.770s	490.250us	50	50	100.00
V2	extclk	clkmgr_extclk	1.430s	214.550us	50	50	100.00
V2	clk_status	clkmgr_clk_status	0.890s	51.188us	50	50	100.00
V2	jitter	clkmgr_smoke	1.200s	149.079us	50	50	100.00
V2	frequency	clkmgr_frequency	7.480s	1.880ms	50	50	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	9.630s	2.057ms	50	50	100.00
V2	frequency_overflow	clkmgr_frequency	7.480s	1.880ms	50	50	100.00
V2	stress_all	clkmgr_stress_all	37.570s	9.877ms	50	50	100.00
V2	intr_test	clkmgr_intr_test			0	0	--
V2	alert_test	clkmgr_alert_test	0.980s	120.310us	50	50	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	3.880s	988.379us	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	3.880s	988.379us	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	0.910s	39.589us	5	5	100.00
		clkmgr_csr_rw	0.990s	80.983us	20	20	100.00
		clkmgr_csr_aliasing	2.230s	367.955us	5	5	100.00
		clkmgr_same_csr_outstanding	2.030s	352.026us	20	20	100.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	0.910s	39.589us	5	5	100.00
		clkmgr_csr_rw	0.990s	80.983us	20	20	100.00
		clkmgr_csr_aliasing	2.230s	367.955us	5	5	100.00
		clkmgr_same_csr_outstanding	2.030s	352.026us	20	20	100.00
V2		TOTAL			440	440	100.00
V2S	tl_intg_err	clkmgr_sec_cm	3.880s	843.197us	5	5	100.00
		clkmgr_tl_intg_err	3.700s	1.047ms	20	20	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	3.140s	875.288us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	3.140s	875.288us	20	20	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	3.140s	875.288us	20	20	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	3.140s	875.288us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	7.080s	2.479ms	20	20	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	3.700s	1.047ms	20	20	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	7.480s	1.880ms	50	50	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	9.630s	2.057ms	50	50	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	3.140s	875.288us	20	20	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	1.170s	42.160us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	clkmgr_lc_ctrl_intersig_mubi	1.070s	136.685us	50	50	100.00
V2S	sec_cm_lc_ctrl_clk_handshake_intersig_mubi	clkmgr_lc_clk_byp_req_intersig_mubi	1.040s	118.086us	50	50	100.00
V2S	sec_cm_clk_handshake_intersig_mubi	clkmgr_clk_handshake_intersig_mubi	1.000s	86.389us	48	50	96.00
V2S	sec_cm_div_intersig_mubi	clkmgr_div_intersig_mubi	1.380s	401.333us	50	50	100.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	0.990s	80.983us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	3.880s	843.197us	5	5	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	0.990s	80.983us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	0.990s	80.983us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	3.880s	843.197us	5	5	100.00
V2S		TOTAL			313	315	99.37
V3	regwen	clkmgr_regwen	4.300s	1.399ms	50	50	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	2.024m	55.020ms	50	50	100.00
V3		TOTAL			100	100	100.00
		TOTAL			958	960	99.79

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	10	10	90.91
V2S	9	9	8	88.89
V3	2	2	2	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.02	99.34	96.34	100.00	100.00	99.17	96.47	87.82

Failure Buckets

• UVM_ERROR (clkmgr_extclk_vseq.sv:99) [clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (* [*] vs * [*]) extclk_status mismatch has 2 failures:
  • Test clkmgr_clk_handshake_intersig_mubi has 2 failures.

    • 10.clkmgr_clk_handshake_intersig_mubi.32058099472002136178493951282530917488839810154076109255938840541756087623393
      Line 81, in log /home/runner/_work/pavona/pavona/scratch/main/clkmgr_top_egret-sim-vcs/10.clkmgr_clk_handshake_intersig_mubi/latest/run.log

        UVM_ERROR @   2869201 ps: (clkmgr_extclk_vseq.sv:99) [uvm_test_top.env.virtual_sequencer.clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (0 [0x0] vs 9 [0x9]) extclk_status mismatch
        UVM_INFO @   2869201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 19.clkmgr_clk_handshake_intersig_mubi.112351197124834663104343656093899826209540667741823600726463904314676834514899
      Line 76, in log /home/runner/_work/pavona/pavona/scratch/main/clkmgr_top_egret-sim-vcs/19.clkmgr_clk_handshake_intersig_mubi/latest/run.log

        UVM_ERROR @  47362396 ps: (clkmgr_extclk_vseq.sv:99) [uvm_test_top.env.virtual_sequencer.clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (3 [0x3] vs 9 [0x9]) extclk_status mismatch
        UVM_INFO @  47362396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---