CSRNG Simulation Results

Saturday June 06 2026 03:15:30 UTC

GitHub Revision: 285e653a0b

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	2.480s	83.057us	5	5	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	2.090s	100.554us	5	5	100.00
V1	csr_rw	csrng_csr_rw	2.250s	98.640us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	21.460s	1.333ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	3.510s	201.249us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	4.210s	344.471us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	2.250s	98.640us	20	20	100.00
		csrng_csr_aliasing	3.510s	201.249us	5	5	100.00
V1		TOTAL			60	60	100.00
V2	interrupts	csrng_intr	14.350s	923.661us	30	30	100.00
V2	alerts	csrng_alert	27.290s	2.498ms	18	18	100.00
V2	err	csrng_err	1.990s	71.780us	70	70	100.00
V2	cmds	csrng_cmds	5.306m	31.568ms	12	12	100.00
V2	life cycle	csrng_cmds	5.306m	31.568ms	12	12	100.00
V2	stress_all	csrng_stress_all	9.852m	33.019ms	5	5	100.00
V2	intr_test	csrng_intr_test	1.820s	148.832us	50	50	100.00
V2	alert_test	csrng_alert_test	4.420s	222.388us	3	3	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	22.540s	2.289ms	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	22.540s	2.289ms	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	2.090s	100.554us	5	5	100.00
		csrng_csr_rw	2.250s	98.640us	20	20	100.00
		csrng_csr_aliasing	3.510s	201.249us	5	5	100.00
		csrng_same_csr_outstanding	2.670s	140.256us	3	3	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	2.090s	100.554us	5	5	100.00
		csrng_csr_rw	2.250s	98.640us	20	20	100.00
		csrng_csr_aliasing	3.510s	201.249us	5	5	100.00
		csrng_same_csr_outstanding	2.670s	140.256us	3	3	100.00
V2		TOTAL			211	211	100.00
V2S	tl_intg_err	csrng_sec_cm	2.900s	95.302us	3	3	100.00
		csrng_tl_intg_err	5.420s	408.362us	8	8	100.00
V2S	sec_cm_config_regwen	csrng_regwen	2.240s	93.502us	3	3	100.00
		csrng_csr_rw	2.250s	98.640us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	27.290s	2.498ms	18	18	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	9.852m	33.019ms	5	5	100.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	14.350s	923.661us	30	30	100.00
		csrng_err	1.990s	71.780us	70	70	100.00
		csrng_sec_cm	2.900s	95.302us	3	3	100.00
V2S	sec_cm_updrsp_fsm_sparse	csrng_intr	14.350s	923.661us	30	30	100.00
		csrng_err	1.990s	71.780us	70	70	100.00
		csrng_sec_cm	2.900s	95.302us	3	3	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	14.350s	923.661us	30	30	100.00
		csrng_err	1.990s	71.780us	70	70	100.00
		csrng_sec_cm	2.900s	95.302us	3	3	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	14.350s	923.661us	30	30	100.00
		csrng_err	1.990s	71.780us	70	70	100.00
		csrng_sec_cm	2.900s	95.302us	3	3	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	14.350s	923.661us	30	30	100.00
		csrng_err	1.990s	71.780us	70	70	100.00
		csrng_sec_cm	2.900s	95.302us	3	3	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	14.350s	923.661us	30	30	100.00
		csrng_err	1.990s	71.780us	70	70	100.00
		csrng_sec_cm	2.900s	95.302us	3	3	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	14.350s	923.661us	30	30	100.00
		csrng_err	1.990s	71.780us	70	70	100.00
		csrng_sec_cm	2.900s	95.302us	3	3	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	14.350s	923.661us	30	30	100.00
		csrng_err	1.990s	71.780us	70	70	100.00
		csrng_sec_cm	2.900s	95.302us	3	3	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	27.290s	2.498ms	18	18	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	14.350s	923.661us	30	30	100.00
		csrng_err	1.990s	71.780us	70	70	100.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	9.852m	33.019ms	5	5	100.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	27.290s	2.498ms	18	18	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	5.420s	408.362us	8	8	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	14.350s	923.661us	30	30	100.00
		csrng_err	1.990s	71.780us	70	70	100.00
		csrng_sec_cm	2.900s	95.302us	3	3	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	14.350s	923.661us	30	30	100.00
		csrng_err	1.990s	71.780us	70	70	100.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	14.350s	923.661us	30	30	100.00
		csrng_err	1.990s	71.780us	70	70	100.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	14.350s	923.661us	30	30	100.00
		csrng_err	1.990s	71.780us	70	70	100.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	14.350s	923.661us	30	30	100.00
		csrng_err	1.990s	71.780us	70	70	100.00
		csrng_sec_cm	2.900s	95.302us	3	3	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	14.350s	923.661us	30	30	100.00
		csrng_err	1.990s	71.780us	70	70	100.00
V2S		TOTAL			14	14	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	3.773m	15.965ms	3	3	100.00
V3		TOTAL			3	3	100.00
		TOTAL			288	288	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	9	100.00
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
90.39	95.00	91.96	99.19	66.31	92.58	95.95	91.73