DMA Simulation Results

Saturday June 06 2026 03:15:30 UTC

GitHub Revision: 285e653a0b

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	5.960s	525.730us	25	25	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	6.610s	634.741us	25	25	100.00
V1	dma_generic_smoke	dma_generic_smoke	6.370s	1.724ms	50	50	100.00
V1	csr_hw_reset	dma_csr_hw_reset	1.120s	65.523us	5	5	100.00
V1	csr_rw	dma_csr_rw	1.100s	57.719us	3	3	100.00
V1	csr_bit_bash	dma_csr_bit_bash	9.580s	4.119ms	5	5	100.00
V1	csr_aliasing	dma_csr_aliasing	6.450s	1.567ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	1.380s	44.631us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	1.100s	57.719us	3	3	100.00
		dma_csr_aliasing	6.450s	1.567ms	5	5	100.00
V1		TOTAL			138	138	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	1.301m	10.788ms	3	3	100.00
V2	dma_memory_tl_error	dma_memory_stress	26.708m	823.795ms	13	13	100.00
V2	dma_handshake_tl_error	dma_handshake_stress	38.880m	205.573ms	11	11	100.00
V2	dma_handshake_stress	dma_handshake_stress	38.880m	205.573ms	11	11	100.00
V2	dma_memory_stress	dma_memory_stress	26.708m	823.795ms	13	13	100.00
V2	dma_generic_stress	dma_generic_stress	31.759m	771.234ms	13	14	92.86
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	38.880m	205.573ms	11	11	100.00
V2	dma_abort	dma_abort	15.150s	5.451ms	5	5	100.00
V2	dma_stress_all	dma_stress_all	3.193m	18.510ms	7	8	87.50
V2	alert_test	dma_alert_test	0.900s	23.945us	3	3	100.00
V2	intr_test	dma_intr_test	0.920s	12.037us	4	4	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	2.480s	269.198us	5	5	100.00
V2	tl_d_illegal_access	dma_tl_errors	2.480s	269.198us	5	5	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	1.120s	65.523us	5	5	100.00
		dma_csr_rw	1.100s	57.719us	3	3	100.00
		dma_csr_aliasing	6.450s	1.567ms	5	5	100.00
		dma_same_csr_outstanding	2.040s	430.368us	20	20	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	1.120s	65.523us	5	5	100.00
		dma_csr_rw	1.100s	57.719us	3	3	100.00
		dma_csr_aliasing	6.450s	1.567ms	5	5	100.00
		dma_same_csr_outstanding	2.040s	430.368us	20	20	100.00
V2		TOTAL			84	86	97.67
V2S	dma_illegal_addr_range	dma_mem_enabled	21.400s	426.230us	17	17	100.00
		dma_generic_stress	31.759m	771.234ms	13	14	92.86
		dma_handshake_stress	38.880m	205.573ms	11	11	100.00
V2S	dma_config_lock	dma_config_lock	7.490s	2.433ms	3	3	100.00
V2S	tl_intg_err	dma_tl_intg_err	3.160s	913.338us	3	3	100.00
		dma_sec_cm	0.910s	104.642us	5	5	100.00
V2S		TOTAL			28	28	100.00
V3		TOTAL			0	0	--
	Unmapped tests	dma_short_transfer	2.123m	14.938ms	16	16	100.00
		dma_longer_transfer	9.210s	2.371ms	5	5	100.00
		dma_stress_all_with_rand_reset	10.890s	1.500ms	0	1	0.00
		TOTAL			271	274	98.91

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	3	3	2	66.67
V1	8	8	8	100.00
V2	10	10	8	80.00
V2S	4	4	4	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
91.74	97.36	95.92	80.45	89.47	95.98	95.86	87.18

Failure Buckets

• UVM_ERROR @ *ps: (cip_base_vseq.sv:1237) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test dma_stress_all_with_rand_reset has 1 failures.

    • 0.dma_stress_all_with_rand_reset.80165049490487635761149666899102538876769791763885146052848115151854121114811
      Line 109, in log /home/runner/_work/pavona/pavona/scratch/main/dma-sim-vcs/0.dma_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1499765725ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10010 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1499765725ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ *ps: (dma_generic_vseq.sv:36) [dma_stress_all_vseq] Check failed (dma_config.is_valid_config) has 1 failures:

  • Test dma_stress_all has 1 failures.

    • 6.dma_stress_all.83498168618085966251534444083199572454111136097567018205511417921272517578078
      Line 541, in log /home/runner/_work/pavona/pavona/scratch/main/dma-sim-vcs/6.dma_stress_all/latest/run.log

        UVM_ERROR @ 18509604342ps: (dma_generic_vseq.sv:36) [uvm_test_top.env.virtual_sequencer.dma_stress_all_vseq] Check failed (dma_config.is_valid_config)
        UVM_INFO @ 18509604342ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ *ps: (dma_generic_vseq.sv:36) [dma_generic_stress_vseq] Check failed (dma_config.is_valid_config) has 1 failures:

  • Test dma_generic_stress has 1 failures.

    • 8.dma_generic_stress.14440332826430883915159194476573541388900477252056665178987499973063272652301
      Line 447, in log /home/runner/_work/pavona/pavona/scratch/main/dma-sim-vcs/8.dma_generic_stress/latest/run.log

        UVM_ERROR @ 197069019620ps: (dma_generic_vseq.sv:36) [uvm_test_top.env.virtual_sequencer.dma_generic_stress_vseq] Check failed (dma_config.is_valid_config)
        UVM_INFO @ 197069019620ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---