EDN/EDN0 Simulation Results

Saturday June 06 2026 03:15:30 UTC

GitHub Revision: 285e653a0b

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	0.710s	30.126us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.980s	27.268us	5	5	100.00
V1	csr_rw	edn_csr_rw	0.960s	23.238us	3	3	100.00
V1	csr_bit_bash	edn_csr_bit_bash	3.770s	376.425us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.090s	51.361us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.080s	99.797us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.960s	23.238us	3	3	100.00
		edn_csr_aliasing	1.090s	51.361us	5	5	100.00
V1		TOTAL			39	39	100.00
V2	firmware	edn_genbits	1.580s	125.747us	11	11	100.00
V2	csrng_commands	edn_genbits	1.580s	125.747us	11	11	100.00
V2	genbits	edn_genbits	1.580s	125.747us	11	11	100.00
V2	interrupts	edn_intr	0.770s	20.445us	9	9	100.00
V2	alerts	edn_alert	0.820s	31.551us	28	28	100.00
V2	errs	edn_err	0.780s	20.125us	8	8	100.00
V2	disable	edn_disable	0.720s	11.196us	14	14	100.00
		edn_disable_auto_req_mode	0.940s	48.551us	10	10	100.00
V2	stress_all	edn_stress_all	2.510s	2.241ms	1	1	100.00
V2	intr_test	edn_intr_test	0.970s	15.105us	50	50	100.00
V2	alert_test	edn_alert_test	0.670s	16.879us	3	3	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	2.710s	113.868us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	2.710s	113.868us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.980s	27.268us	5	5	100.00
		edn_csr_rw	0.960s	23.238us	3	3	100.00
		edn_csr_aliasing	1.090s	51.361us	5	5	100.00
		edn_same_csr_outstanding	1.210s	40.898us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.980s	27.268us	5	5	100.00
		edn_csr_rw	0.960s	23.238us	3	3	100.00
		edn_csr_aliasing	1.090s	51.361us	5	5	100.00
		edn_same_csr_outstanding	1.210s	40.898us	20	20	100.00
V2		TOTAL			174	174	100.00
V2S	tl_intg_err	edn_sec_cm	3.160s	590.560us	3	3	100.00
		edn_tl_intg_err	1.960s	434.675us	3	3	100.00
V2S	sec_cm_config_regwen	edn_regwen	0.710s	21.089us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	0.820s	31.551us	28	28	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	3.160s	590.560us	3	3	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	3.160s	590.560us	3	3	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	3.160s	590.560us	3	3	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	3.160s	590.560us	3	3	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	0.820s	31.551us	28	28	100.00
		edn_sec_cm	3.160s	590.560us	3	3	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	0.820s	31.551us	28	28	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	1.960s	434.675us	3	3	100.00
V2S		TOTAL			16	16	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	35.720s	3.009ms	5	5	100.00
V3		TOTAL			5	5	100.00
		TOTAL			234	234	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.48	98.91	94.14	97.12	84.41	96.51	97.61	92.66