EDN/EDN1 Simulation Results

Saturday June 06 2026 03:15:30 UTC

GitHub Revision: 285e653a0b

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	0.760s	16.142us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.760s	44.321us	5	5	100.00
V1	csr_rw	edn_csr_rw	0.670s	30.205us	3	3	100.00
V1	csr_bit_bash	edn_csr_bit_bash	1.800s	200.060us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	0.970s	39.216us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.010s	50.844us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.670s	30.205us	3	3	100.00
		edn_csr_aliasing	0.970s	39.216us	5	5	100.00
V1		TOTAL			39	39	100.00
V2	firmware	edn_genbits	2.580s	146.143us	11	11	100.00
V2	csrng_commands	edn_genbits	2.580s	146.143us	11	11	100.00
V2	genbits	edn_genbits	2.580s	146.143us	11	11	100.00
V2	interrupts	edn_intr	1.010s	33.260us	8	8	100.00
V2	alerts	edn_alert	1.170s	172.832us	26	26	100.00
V2	errs	edn_err	0.910s	23.045us	8	8	100.00
V2	disable	edn_disable	0.880s	18.509us	8	8	100.00
		edn_disable_auto_req_mode	0.980s	41.693us	11	11	100.00
V2	stress_all	edn_stress_all	3.070s	467.944us	3	3	100.00
V2	intr_test	edn_intr_test	0.820s	55.774us	50	50	100.00
V2	alert_test	edn_alert_test	0.840s	81.711us	3	3	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	1.610s	158.516us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	1.610s	158.516us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.760s	44.321us	5	5	100.00
		edn_csr_rw	0.670s	30.205us	3	3	100.00
		edn_csr_aliasing	0.970s	39.216us	5	5	100.00
		edn_same_csr_outstanding	0.850s	25.471us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.760s	44.321us	5	5	100.00
		edn_csr_rw	0.670s	30.205us	3	3	100.00
		edn_csr_aliasing	0.970s	39.216us	5	5	100.00
		edn_same_csr_outstanding	0.850s	25.471us	20	20	100.00
V2		TOTAL			168	168	100.00
V2S	tl_intg_err	edn_sec_cm	2.950s	316.511us	3	3	100.00
		edn_tl_intg_err	1.680s	141.925us	3	3	100.00
V2S	sec_cm_config_regwen	edn_regwen	0.710s	19.329us	3	3	100.00
V2S	sec_cm_config_mubi	edn_alert	1.170s	172.832us	26	26	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	2.950s	316.511us	3	3	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	2.950s	316.511us	3	3	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	2.950s	316.511us	3	3	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	2.950s	316.511us	3	3	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.170s	172.832us	26	26	100.00
		edn_sec_cm	2.950s	316.511us	3	3	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.170s	172.832us	26	26	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	1.680s	141.925us	3	3	100.00
V2S		TOTAL			9	9	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	34.880s	5.972ms	5	5	100.00
V3		TOTAL			5	5	100.00
		TOTAL			221	221	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.28	98.48	94.77	96.15	86.36	94.59	97.14	92.44