ENTROPY_SRC/RNG16BITS Simulation Results

Saturday June 06 2026 03:15:30 UTC

GitHub Revision: 285e653a0b

Branch: main

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 0.840s 39.641us 1 1 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 1.070s 41.231us 3 3 100.00
V1 csr_rw entropy_src_csr_rw 0.930s 51.351us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 7.260s 1.054ms 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 2.730s 838.152us 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 1.160s 27.468us 3 3 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 0.930s 51.351us 20 20 100.00
entropy_src_csr_aliasing 2.730s 838.152us 5 5 100.00
V1 TOTAL 37 37 100.00
V2 firmware entropy_src_smoke 0.840s 39.641us 1 1 100.00
entropy_src_rng 7.860m 18.020ms 56 57 98.25
entropy_src_fw_ov 7.966m 20.024ms 24 24 100.00
V2 firmware_mode entropy_src_fw_ov 7.966m 20.024ms 24 24 100.00
V2 rng_mode entropy_src_rng 7.860m 18.020ms 56 57 98.25
V2 rng_max_rate entropy_src_rng_max_rate 11.998m 18.069ms 59 59 100.00
V2 health_checks entropy_src_rng 7.860m 18.020ms 56 57 98.25
V2 conditioning entropy_src_rng 7.860m 18.020ms 56 57 98.25
V2 interrupts entropy_src_rng 7.860m 18.020ms 56 57 98.25
entropy_src_intr 24.030s 980.659us 12 12 100.00
V2 alerts entropy_src_rng 7.860m 18.020ms 56 57 98.25
entropy_src_functional_alerts 4.620s 178.603us 3 3 100.00
V2 stress_all entropy_src_stress_all 10.776m 17.155ms 6 6 100.00
V2 functional_errors entropy_src_functional_errors 1.236m 10.012ms 190 192 98.96
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 1.440s 82.670us 1 1 100.00
V2 intr_test entropy_src_intr_test 0.850s 55.533us 50 50 100.00
V2 alert_test entropy_src_alert_test 1.110s 18.169us 3 3 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 2.960s 659.232us 5 5 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 2.960s 659.232us 5 5 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 1.070s 41.231us 3 3 100.00
entropy_src_csr_rw 0.930s 51.351us 20 20 100.00
entropy_src_csr_aliasing 2.730s 838.152us 5 5 100.00
entropy_src_same_csr_outstanding 1.410s 90.949us 3 3 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 1.070s 41.231us 3 3 100.00
entropy_src_csr_rw 0.930s 51.351us 20 20 100.00
entropy_src_csr_aliasing 2.730s 838.152us 5 5 100.00
entropy_src_same_csr_outstanding 1.410s 90.949us 3 3 100.00
V2 TOTAL 412 415 99.28
V2S tl_intg_err entropy_src_sec_cm 1.750s 309.821us 3 3 100.00
entropy_src_tl_intg_err 2.790s 4.428ms 14 14 100.00
V2S sec_cm_config_regwen entropy_src_rng 7.860m 18.020ms 56 57 98.25
entropy_src_cfg_regwen 1.110s 27.303us 3 3 100.00
V2S sec_cm_config_mubi entropy_src_rng 7.860m 18.020ms 56 57 98.25
V2S sec_cm_config_redun entropy_src_rng 7.860m 18.020ms 56 57 98.25
V2S sec_cm_intersig_mubi entropy_src_rng 7.860m 18.020ms 56 57 98.25
entropy_src_fw_ov 7.966m 20.024ms 24 24 100.00
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 1.236m 10.012ms 190 192 98.96
entropy_src_sec_cm 1.750s 309.821us 3 3 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 1.236m 10.012ms 190 192 98.96
entropy_src_sec_cm 1.750s 309.821us 3 3 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 7.860m 18.020ms 56 57 98.25
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 1.236m 10.012ms 190 192 98.96
entropy_src_sec_cm 1.750s 309.821us 3 3 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 1.236m 10.012ms 190 192 98.96
entropy_src_sec_cm 1.750s 309.821us 3 3 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 1.236m 10.012ms 190 192 98.96
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 4.620s 178.603us 3 3 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 2.790s 4.428ms 14 14 100.00
V2S TOTAL 20 20 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 7.054m 19.031ms 11 11 100.00
V3 stress_all_with_rand_reset entropy_src_stress_all_with_rand_reset 0 0 --
V3 TOTAL 11 11 100.00
TOTAL 480 483 99.38

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 12 12 10 83.33
V2S 3 3 3 100.00
V3 2 1 1 50.00

Coverage Results

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
86.57 97.56 90.00 77.46 62.07 95.55 89.57 93.78

Failure Buckets