ENTROPY_SRC/RNG4BITS Simulation Results

Saturday June 06 2026 03:15:30 UTC

GitHub Revision: 285e653a0b

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	entropy_src_smoke	1.190s	24.642us	1	1	100.00
V1	csr_hw_reset	entropy_src_csr_hw_reset	1.220s	25.060us	7	7	100.00
V1	csr_rw	entropy_src_csr_rw	1.020s	74.541us	3	3	100.00
V1	csr_bit_bash	entropy_src_csr_bit_bash	6.400s	1.540ms	5	5	100.00
V1	csr_aliasing	entropy_src_csr_aliasing	2.580s	1.978ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	entropy_src_csr_mem_rw_with_rand_reset	1.560s	179.316us	3	3	100.00
V1	regwen_csr_and_corresponding_lockable_csr	entropy_src_csr_rw	1.020s	74.541us	3	3	100.00
		entropy_src_csr_aliasing	2.580s	1.978ms	5	5	100.00
V1		TOTAL			24	24	100.00
V2	firmware	entropy_src_smoke	1.190s	24.642us	1	1	100.00
		entropy_src_rng	5.388m	20.060ms	45	45	100.00
		entropy_src_fw_ov	5.310m	19.025ms	22	25	88.00
V2	firmware_mode	entropy_src_fw_ov	5.310m	19.025ms	22	25	88.00
V2	rng_mode	entropy_src_rng	5.388m	20.060ms	45	45	100.00
V2	rng_max_rate	entropy_src_rng_max_rate	9.977m	20.068ms	70	70	100.00
V2	health_checks	entropy_src_rng	5.388m	20.060ms	45	45	100.00
V2	conditioning	entropy_src_rng	5.388m	20.060ms	45	45	100.00
V2	interrupts	entropy_src_rng	5.388m	20.060ms	45	45	100.00
		entropy_src_intr	20.110s	1.955ms	11	11	100.00
V2	alerts	entropy_src_rng	5.388m	20.060ms	45	45	100.00
		entropy_src_functional_alerts	3.600s	279.932us	3	3	100.00
V2	stress_all	entropy_src_stress_all	3.429m	18.276ms	5	5	100.00
V2	functional_errors	entropy_src_functional_errors	1.420s	49.529us	67	67	100.00
V2	firmware_ov_read_contiguous_data	entropy_src_fw_ov_contiguous	1.980s	136.012us	1	1	100.00
V2	intr_test	entropy_src_intr_test	1.020s	19.076us	3	3	100.00
V2	alert_test	entropy_src_alert_test	1.030s	21.079us	3	3	100.00
V2	tl_d_oob_addr_access	entropy_src_tl_errors	2.580s	280.914us	6	6	100.00
V2	tl_d_illegal_access	entropy_src_tl_errors	2.580s	280.914us	6	6	100.00
V2	tl_d_outstanding_access	entropy_src_csr_hw_reset	1.220s	25.060us	7	7	100.00
		entropy_src_csr_rw	1.020s	74.541us	3	3	100.00
		entropy_src_csr_aliasing	2.580s	1.978ms	5	5	100.00
		entropy_src_same_csr_outstanding	1.880s	82.105us	20	20	100.00
V2	tl_d_partial_access	entropy_src_csr_hw_reset	1.220s	25.060us	7	7	100.00
		entropy_src_csr_rw	1.020s	74.541us	3	3	100.00
		entropy_src_csr_aliasing	2.580s	1.978ms	5	5	100.00
		entropy_src_same_csr_outstanding	1.880s	82.105us	20	20	100.00
V2		TOTAL			256	259	98.84
V2S	tl_intg_err	entropy_src_sec_cm	1.710s	167.421us	3	3	100.00
		entropy_src_tl_intg_err	3.080s	171.161us	17	17	100.00
V2S	sec_cm_config_regwen	entropy_src_rng	5.388m	20.060ms	45	45	100.00
		entropy_src_cfg_regwen	1.110s	23.061us	3	3	100.00
V2S	sec_cm_config_mubi	entropy_src_rng	5.388m	20.060ms	45	45	100.00
V2S	sec_cm_config_redun	entropy_src_rng	5.388m	20.060ms	45	45	100.00
V2S	sec_cm_intersig_mubi	entropy_src_rng	5.388m	20.060ms	45	45	100.00
		entropy_src_fw_ov	5.310m	19.025ms	22	25	88.00
V2S	sec_cm_main_sm_fsm_sparse	entropy_src_functional_errors	1.420s	49.529us	67	67	100.00
		entropy_src_sec_cm	1.710s	167.421us	3	3	100.00
V2S	sec_cm_ack_sm_fsm_sparse	entropy_src_functional_errors	1.420s	49.529us	67	67	100.00
		entropy_src_sec_cm	1.710s	167.421us	3	3	100.00
V2S	sec_cm_rng_bkgn_chk	entropy_src_rng	5.388m	20.060ms	45	45	100.00
V2S	sec_cm_fifo_ctr_redun	entropy_src_functional_errors	1.420s	49.529us	67	67	100.00
		entropy_src_sec_cm	1.710s	167.421us	3	3	100.00
V2S	sec_cm_ctr_redun	entropy_src_functional_errors	1.420s	49.529us	67	67	100.00
		entropy_src_sec_cm	1.710s	167.421us	3	3	100.00
V2S	sec_cm_ctr_local_esc	entropy_src_functional_errors	1.420s	49.529us	67	67	100.00
V2S	sec_cm_esfinal_rdata_bus_consistency	entropy_src_functional_alerts	3.600s	279.932us	3	3	100.00
V2S	sec_cm_tile_link_bus_integrity	entropy_src_tl_intg_err	3.080s	171.161us	17	17	100.00
V2S		TOTAL			23	23	100.00
V3	external_health_tests	entropy_src_rng_with_xht_rsps	4.426m	17.014ms	16	16	100.00
V3	stress_all_with_rand_reset	entropy_src_stress_all_with_rand_reset			0	0	--
V3		TOTAL			16	16	100.00
		TOTAL			319	322	99.07

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	11	91.67
V2S	3	3	3	100.00
V3	2	1	1	50.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
86.47	97.04	91.96	74.13	62.07	94.69	89.36	96.01

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_alert did not trigger max_delay:* has 3 failures:
  • Test entropy_src_fw_ov has 3 failures.

    • 19.entropy_src_fw_ov.29010387844878150792517346452268457340972162093168846092524690132374375528093
      Line 701, in log /home/runner/_work/pavona/pavona/scratch/main/entropy_src_rng4bits-sim-vcs/19.entropy_src_fw_ov/latest/run.log

        UVM_ERROR @ 2288483463 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_alert did not trigger max_delay:4
        UVM_INFO @ 2288483463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 20.entropy_src_fw_ov.78039940374029356621006483907617602506261500918887564714169998470043512893911
      Line 701, in log /home/runner/_work/pavona/pavona/scratch/main/entropy_src_rng4bits-sim-vcs/20.entropy_src_fw_ov/latest/run.log

        UVM_ERROR @ 4924781964 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_alert did not trigger max_delay:4
        UVM_INFO @ 4924781964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.