FLASH_CTRL/EGRET Simulation Results

Saturday June 06 2026 03:15:30 UTC

GitHub Revision: 285e653a0b

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	1.994m	41.089us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	19.440s	24.286us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	32.640s	240.168us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	12.140s	488.506us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	50.330s	18.187ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	35.840s	6.813ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	14.220s	48.490us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	12.140s	488.506us	20	20	100.00
		flash_ctrl_csr_aliasing	35.840s	6.813ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	8.490s	26.027us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	10.120s	33.809us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	19.430s	24.525us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	45.270s	151.076us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	25.591m	679.989ms	3	3	100.00
		flash_ctrl_hw_rma_reset	10.157m	420.245ms	20	20	100.00
		flash_ctrl_lcmgr_intg	10.370s	23.616us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	24.818m	242.556ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	3.991m	8.502ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	2.158m	10.991ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	39.675m	48.916ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	1.349m	1.412ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	23.800s	18.285us	36	40	90.00
		flash_ctrl_rw_evict_all_en	23.830s	29.374us	39	40	97.50
		flash_ctrl_re_evict	27.520s	150.549us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	3.326m	5.135ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	3.326m	5.135ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	8.649m	21.945ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	20.450s	456.583us	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	8.997m	8.934ms	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	13.385m	6.214ms	9	10	90.00
V2	error_prog_win	flash_ctrl_error_prog_win	6.705m	8.480ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	17.472m	11.392ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	10.240s	33.543us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	2.580m	7.051ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	16.870s	66.966us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	12.370s	15.011us	0	80	0.00
V2	stress_all	flash_ctrl_stress_all	10.063m	357.841us	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	2.542m	2.768ms	50	50	100.00
		flash_ctrl_otp_reset	1.597m	41.672us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	25.591m	679.989ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	2.255m	7.093ms	39	40	97.50
		flash_ctrl_intr_wr	1.137m	11.395ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	3.331m	51.542ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	4.064m	228.167ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	50.230s	3.840ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	56.700s	974.478us	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	16.370s	33.664us	5	5	100.00
		flash_ctrl_ro_derr	1.713m	715.962us	10	10	100.00
		flash_ctrl_rw_derr	2.662m	9.475ms	10	10	100.00
		flash_ctrl_derr_detect	2.209m	1.349ms	5	5	100.00
		flash_ctrl_integrity	6.622m	17.141ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	17.430s	90.392us	5	5	100.00
		flash_ctrl_ro_serr	1.654m	1.406ms	10	10	100.00
		flash_ctrl_rw_serr	2.875m	7.466ms	10	10	100.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.131m	3.667ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.180m	1.803ms	5	5	100.00
V2	scramble	flash_ctrl_wo	2.772m	21.182ms	20	20	100.00
		flash_ctrl_write_word_sweep	9.470s	79.811us	1	1	100.00
		flash_ctrl_read_word_sweep	5.150s	46.630us	1	1	100.00
		flash_ctrl_ro	1.404m	1.199ms	20	20	100.00
		flash_ctrl_rw	6.458m	38.426ms	19	20	95.00
V2	filesystem_support	flash_ctrl_fs_sup	30.470s	6.640ms	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	9.491m	49.753ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	2.700m	10.020ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	10.500s	107.819us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	9.330s	24.652us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	14.020s	106.110us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	14.020s	106.110us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	32.640s	240.168us	5	5	100.00
		flash_ctrl_csr_rw	12.140s	488.506us	20	20	100.00
		flash_ctrl_csr_aliasing	35.840s	6.813ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	17.640s	889.511us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	32.640s	240.168us	5	5	100.00
		flash_ctrl_csr_rw	12.140s	488.506us	20	20	100.00
		flash_ctrl_csr_aliasing	35.840s	6.813ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	17.640s	889.511us	20	20	100.00
V2		TOTAL			925	1013	91.31
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	43.770s	46.573us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	43.770s	46.573us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	43.770s	46.573us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	43.770s	46.573us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	47.340s	1.588ms	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	2.527m	253.320us	0	5	0.00
		flash_ctrl_tl_intg_err	32.720s	92.156us	0	20	0.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	32.720s	92.156us	0	20	0.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	32.720s	92.156us	0	20	0.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	24.390s	217.619us	3	3	100.00
		flash_ctrl_wr_intg	11.060s	49.743us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	1.994m	41.089us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	1.597m	41.672us	80	80	100.00
		flash_ctrl_disable	16.870s	66.966us	50	50	100.00
		flash_ctrl_sec_info_access	52.630s	30.999ms	50	50	100.00
		flash_ctrl_connect	12.370s	15.011us	0	80	0.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	10.220s	40.330us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	12.140s	488.506us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	43.770s	46.573us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	12.140s	488.506us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	43.770s	46.573us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	12.140s	488.506us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	43.770s	46.573us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	16.870s	66.966us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	24.390s	217.619us	3	3	100.00
		flash_ctrl_access_after_disable	10.360s	133.777us	3	3	100.00
V2S	sec_cm_mem_addr_infection	flash_ctrl_host_addr_infection	19.430s	66.373us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	16.870s	66.966us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	20.450s	456.583us	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	6.458m	38.426ms	19	20	95.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	2.875m	7.466ms	10	10	100.00
		flash_ctrl_rw_derr	2.662m	9.475ms	10	10	100.00
		flash_ctrl_integrity	6.622m	17.141ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	25.591m	679.989ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	2.527m	253.320us	0	5	0.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	2.527m	253.320us	0	5	0.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	2.527m	253.320us	0	5	0.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	2.527m	253.320us	0	5	0.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	14.410s	923.286us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	10.490s	66.655us	4	5	80.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	9.740s	70.839us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	2.527m	253.320us	0	5	0.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	2.527m	253.320us	0	5	0.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	2.527m	253.320us	0	5	0.00
V2S		TOTAL			121	147	82.31
V3	asymmetric_read_path	flash_ctrl_rd_ooo	33.440s	319.480us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
	Unmapped tests	flash_ctrl_basic_rw	6.989m	4.225ms	3	3	100.00
		TOTAL			1170	1284	91.12

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	9	9	9	100.00
V2	55	55	49	89.09
V2S	13	13	10	76.92
V3	2	1	1	50.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.77	95.60	94.08	95.39	90.43	96.74	94.41	96.75

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1268) [UVM/DPI/HDL_FORCE] set: unable to locate hdl path (tb.dut.cio_tck_i) has 80 failures:

  • Test flash_ctrl_connect has 80 failures.

    • 0.flash_ctrl_connect.87250171627578117080569252527651565375836209102895498298105217061984671554343
      Line 119, in log /home/runner/_work/pavona/pavona/scratch/main/flash_ctrl_top_egret-sim-vcs/0.flash_ctrl_connect/latest/run.log

        UVM_ERROR @ 3885.7 ns: (uvm_hdl_vcs.c:1268) [UVM/DPI/HDL_FORCE] set: unable to locate hdl path (tb.dut.cio_tck_i)
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_INFO @ 3885.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • 1.flash_ctrl_connect.15833154476838253751045132424146699170259802532841126190892293916618944103864
      Line 119, in log /home/runner/_work/pavona/pavona/scratch/main/flash_ctrl_top_egret-sim-vcs/1.flash_ctrl_connect/latest/run.log

        UVM_ERROR @ 11427.6 ns: (uvm_hdl_vcs.c:1268) [UVM/DPI/HDL_FORCE] set: unable to locate hdl path (tb.dut.cio_tck_i)
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_INFO @ 11427.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • ... and 78 more failures.

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.std_fault_status.reg_intg_err reset value: * has 15 failures:

  • Test flash_ctrl_tl_intg_err has 11 failures.

    • 0.flash_ctrl_tl_intg_err.90269179967236509571810565520106281148912235466439555747193049336015794532801
      Line 149, in log /home/runner/_work/pavona/pavona/scratch/main/flash_ctrl_top_egret-sim-vcs/0.flash_ctrl_tl_intg_err/latest/run.log

        UVM_ERROR @ 84999.2 ns: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.std_fault_status.reg_intg_err reset value: 0x0
        UVM_INFO @ 84999.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.flash_ctrl_tl_intg_err.9430069355751040612118952935114605208744293702744038987067716835783753256209
      Line 153, in log /home/runner/_work/pavona/pavona/scratch/main/flash_ctrl_top_egret-sim-vcs/1.flash_ctrl_tl_intg_err/latest/run.log

        UVM_ERROR @ 18137.7 ns: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.std_fault_status.reg_intg_err reset value: 0x0
        UVM_INFO @ 18137.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 9 more failures.

  • Test flash_ctrl_sec_cm has 4 failures.

    • 1.flash_ctrl_sec_cm.55355881342667966861317355055587653403726428013232716291153235831255814401312
      Line 364, in log /home/runner/_work/pavona/pavona/scratch/main/flash_ctrl_top_egret-sim-vcs/1.flash_ctrl_sec_cm/latest/run.log

        UVM_ERROR @ 65493.4 ns: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.std_fault_status.reg_intg_err reset value: 0x0
        UVM_INFO @ 65493.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.flash_ctrl_sec_cm.19356538579534172129024614290254841674392620204404558894794379656787229178622
      Line 896, in log /home/runner/_work/pavona/pavona/scratch/main/flash_ctrl_top_egret-sim-vcs/2.flash_ctrl_sec_cm/latest/run.log

        UVM_ERROR @ 253320.3 ns: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.std_fault_status.reg_intg_err reset value: 0x0
        UVM_INFO @ 253320.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 2 more failures.

• UVM_ERROR (cip_base_vseq.sv:1023) virtual_sequencer [flash_ctrl_common_vseq] expect alert:fatal_std_err to fire has 10 failures:

  • Test flash_ctrl_sec_cm has 1 failures.

    • 0.flash_ctrl_sec_cm.29543242167058601026285462690614591084381568578261520244814266644665511928191
      Line 594, in log /home/runner/_work/pavona/pavona/scratch/main/flash_ctrl_top_egret-sim-vcs/0.flash_ctrl_sec_cm/latest/run.log

        UVM_ERROR @ 60977.2 ns: (cip_base_vseq.sv:1023) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.flash_ctrl_common_vseq] expect alert:fatal_std_err to fire
        UVM_INFO @ 60977.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test flash_ctrl_tl_intg_err has 9 failures.

    • 3.flash_ctrl_tl_intg_err.41899128585157948922669152631507868332967292577480094949557624487725404521318
      Line 152, in log /home/runner/_work/pavona/pavona/scratch/main/flash_ctrl_top_egret-sim-vcs/3.flash_ctrl_tl_intg_err/latest/run.log

        UVM_ERROR @ 79265.6 ns: (cip_base_vseq.sv:1023) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.flash_ctrl_common_vseq] expect alert:fatal_std_err to fire
        UVM_INFO @ 79265.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 8.flash_ctrl_tl_intg_err.87888029354199328273447260546247593527753006546033244309285510173728564367032
      Line 159, in log /home/runner/_work/pavona/pavona/scratch/main/flash_ctrl_top_egret-sim-vcs/8.flash_ctrl_tl_intg_err/latest/run.log

        UVM_ERROR @ 35555.3 ns: (cip_base_vseq.sv:1023) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.flash_ctrl_common_vseq] expect alert:fatal_std_err to fire
        UVM_INFO @ 35555.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 7 more failures.

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: * has 4 failures:

  • Test flash_ctrl_rw_evict has 4 failures.

    • 13.flash_ctrl_rw_evict.3249085915004419375934164363676643356620444133704309223845920271986765175159
      Line 119, in log /home/runner/_work/pavona/pavona/scratch/main/flash_ctrl_top_egret-sim-vcs/13.flash_ctrl_rw_evict/latest/run.log

        UVM_ERROR @ 48906.9 ns: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: 0x0
        UVM_INFO @ 48906.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 14.flash_ctrl_rw_evict.73184199129474632476241975006011592375658357305011380381121906767144184240361
      Line 119, in log /home/runner/_work/pavona/pavona/scratch/main/flash_ctrl_top_egret-sim-vcs/14.flash_ctrl_rw_evict/latest/run.log

        UVM_ERROR @ 18285.0 ns: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: 0x0
        UVM_INFO @ 18285.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 2 more failures.

• Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))' has 1 failures:

  • Test flash_ctrl_phy_host_grant_err has 1 failures.

    • 0.flash_ctrl_phy_host_grant_err.73688376282821510380589895585158376053466882335700408346511381645438491503274
      Line 136, in log /home/runner/_work/pavona/pavona/scratch/main/flash_ctrl_top_egret-sim-vcs/0.flash_ctrl_phy_host_grant_err/latest/run.log

            Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))'
        UVM_ERROR @ 9911.5 ns: (alert_esc_if.sv:202) [ASSERT FAILED] AlertKnown_A
        UVM_INFO @ 9911.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (flash_ctrl_env_cfg.sv:714) [cfg] Check failed data[i] === exp_data[i] (* [*] vs * [*]) has 1 failures:

  • Test flash_ctrl_error_mp has 1 failures.

    • 4.flash_ctrl_error_mp.5180550806381591438085489003800310507158614759334438280911884965992083335134
      Line 210, in log /home/runner/_work/pavona/pavona/scratch/main/flash_ctrl_top_egret-sim-vcs/4.flash_ctrl_error_mp/latest/run.log

        UVM_ERROR @ 1442407.6 ns: (flash_ctrl_env_cfg.sv:714) [cfg] Check failed data[i] === exp_data[i] (0x741cdee6 [1110100000111001101111011100110] vs 0xe60e08d8 [11100110000011100000100011011000])
        UVM_INFO @ 1442407.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:267) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 1 failures:

  • Test flash_ctrl_rw has 1 failures.

    • 4.flash_ctrl_rw.6087206742617550757080044179782165384704054672811428859770651902643190630464
      Line 119, in log /home/runner/_work/pavona/pavona/scratch/main/flash_ctrl_top_egret-sim-vcs/4.flash_ctrl_rw/latest/run.log

        UVM_ERROR @ 6092534.7 ns: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
        UVM_INFO @ 6092534.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] *: obs:exp *f0dbfe_381406c3:ffffffff_381406c* mismatch!! has 1 failures:

  • Test flash_ctrl_intr_rd has 1 failures.

    • 19.flash_ctrl_intr_rd.83539444187990697145778040478007075737093481011272573840488522984840757146511
      Line 119, in log /home/runner/_work/pavona/pavona/scratch/main/flash_ctrl_top_egret-sim-vcs/19.flash_ctrl_intr_rd/latest/run.log

        UVM_ERROR @ 341260.8 ns: (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1]    3: obs:exp    85f0dbfe_381406c3:ffffffff_381406c3  mismatch!!
        UVM_INFO @ 341260.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 1 failures:

  • Test flash_ctrl_rw_evict_all_en has 1 failures.

    • 20.flash_ctrl_rw_evict_all_en.93222993448717593499513226335041731683829114579752846329872614353133290280562
      Line 119, in log /home/runner/_work/pavona/pavona/scratch/main/flash_ctrl_top_egret-sim-vcs/20.flash_ctrl_rw_evict_all_en/latest/run.log

        UVM_ERROR @ 11656.9 ns: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
        UVM_INFO @ 11656.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---