HMAC Simulation Results

Saturday June 06 2026 03:15:30 UTC

GitHub Revision: 285e653a0b

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	3.000s	296.831us	1	1	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	0.940s	81.090us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.850s	320.131us	3	3	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	7.910s	4.567ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	6.010s	2.338ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	6.917m	69.313ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.850s	320.131us	3	3	100.00
		hmac_csr_aliasing	6.010s	2.338ms	5	5	100.00
V1		TOTAL			39	39	100.00
V2	long_msg	hmac_long_msg	1.044m	5.117ms	1	1	100.00
V2	back_pressure	hmac_back_pressure	1.053m	1.209ms	3	3	100.00
V2	test_vectors	hmac_test_sha256_vectors	2.932m	9.312ms	11	11	100.00
		hmac_test_sha384_vectors	6.947m	13.885ms	24	24	100.00
		hmac_test_sha512_vectors	6.317m	12.786ms	26	26	100.00
		hmac_test_hmac256_vectors	10.670s	2.562ms	20	20	100.00
		hmac_test_hmac384_vectors	12.370s	1.864ms	29	29	100.00
		hmac_test_hmac512_vectors	15.130s	433.559us	32	32	100.00
V2	burst_wr	hmac_burst_wr	26.840s	640.858us	4	4	100.00
V2	datapath_stress	hmac_datapath_stress	10.669m	4.467ms	1	1	100.00
V2	error	hmac_error	1.400m	39.303ms	1	1	100.00
V2	wipe_secret	hmac_wipe_secret	1.140m	7.830ms	1	1	100.00
V2	save_and_restore	hmac_smoke	3.000s	296.831us	1	1	100.00
		hmac_long_msg	1.044m	5.117ms	1	1	100.00
		hmac_back_pressure	1.053m	1.209ms	3	3	100.00
		hmac_datapath_stress	10.669m	4.467ms	1	1	100.00
		hmac_burst_wr	26.840s	640.858us	4	4	100.00
		hmac_stress_all	19.704m	95.450ms	9	9	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	3.000s	296.831us	1	1	100.00
		hmac_long_msg	1.044m	5.117ms	1	1	100.00
		hmac_back_pressure	1.053m	1.209ms	3	3	100.00
		hmac_datapath_stress	10.669m	4.467ms	1	1	100.00
		hmac_wipe_secret	1.140m	7.830ms	1	1	100.00
		hmac_test_sha256_vectors	2.932m	9.312ms	11	11	100.00
		hmac_test_sha384_vectors	6.947m	13.885ms	24	24	100.00
		hmac_test_sha512_vectors	6.317m	12.786ms	26	26	100.00
		hmac_test_hmac256_vectors	10.670s	2.562ms	20	20	100.00
		hmac_test_hmac384_vectors	12.370s	1.864ms	29	29	100.00
		hmac_test_hmac512_vectors	15.130s	433.559us	32	32	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	3.000s	296.831us	1	1	100.00
		hmac_long_msg	1.044m	5.117ms	1	1	100.00
		hmac_back_pressure	1.053m	1.209ms	3	3	100.00
		hmac_datapath_stress	10.669m	4.467ms	1	1	100.00
		hmac_burst_wr	26.840s	640.858us	4	4	100.00
		hmac_error	1.400m	39.303ms	1	1	100.00
		hmac_wipe_secret	1.140m	7.830ms	1	1	100.00
		hmac_test_sha256_vectors	2.932m	9.312ms	11	11	100.00
		hmac_test_sha384_vectors	6.947m	13.885ms	24	24	100.00
		hmac_test_sha512_vectors	6.317m	12.786ms	26	26	100.00
		hmac_test_hmac256_vectors	10.670s	2.562ms	20	20	100.00
		hmac_test_hmac384_vectors	12.370s	1.864ms	29	29	100.00
		hmac_test_hmac512_vectors	15.130s	433.559us	32	32	100.00
		hmac_stress_all	19.704m	95.450ms	9	9	100.00
V2	stress_all	hmac_stress_all	19.704m	95.450ms	9	9	100.00
V2	alert_test	hmac_alert_test	0.610s	13.583us	3	3	100.00
V2	intr_test	hmac_intr_test	0.700s	39.955us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	2.720s	190.700us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	2.720s	190.700us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	0.940s	81.090us	5	5	100.00
		hmac_csr_rw	0.850s	320.131us	3	3	100.00
		hmac_csr_aliasing	6.010s	2.338ms	5	5	100.00
		hmac_same_csr_outstanding	2.250s	2.136ms	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	0.940s	81.090us	5	5	100.00
		hmac_csr_rw	0.850s	320.131us	3	3	100.00
		hmac_csr_aliasing	6.010s	2.338ms	5	5	100.00
		hmac_same_csr_outstanding	2.250s	2.136ms	20	20	100.00
V2		TOTAL			255	255	100.00
V2S	tl_intg_err	hmac_sec_cm	1.020s	98.765us	3	3	100.00
		hmac_tl_intg_err	3.760s	536.319us	5	5	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	3.760s	536.319us	5	5	100.00
V2S		TOTAL			8	8	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	3.000s	296.831us	1	1	100.00
V3	stress_reset	hmac_stress_reset	4.160s	120.559us	3	3	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	5.799m	9.001ms	10	10	100.00
V3		TOTAL			13	13	100.00
	Unmapped tests	hmac_directed	1.980s	344.002us	3	3	100.00
		TOTAL			318	318	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	6	6	6	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	2	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.31	99.59	96.45	100.00	97.14	97.59	97.36	100.00