285e653a0b| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 11.190s | 1.403ms | 1 | 1 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 12.870s | 773.293us | 5 | 5 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.560s | 24.929us | 3 | 3 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.620s | 193.436us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 2.660s | 521.894us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 1.030s | 44.816us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 0.850s | 58.257us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.620s | 193.436us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 1.030s | 44.816us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 59 | 59 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 1.650s | 658.536us | 2 | 5 | 40.00 |
| V2 | host_stress_all | i2c_host_stress_all | 23.466m | 16.650ms | 5 | 8 | 62.50 |
| V2 | host_maxperf | i2c_host_perf | 5.625m | 12.281ms | 5 | 5 | 100.00 |
| V2 | host_override | i2c_host_override | 0.730s | 18.120us | 4 | 4 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 1.168m | 8.604ms | 1 | 1 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 39.570s | 2.582ms | 1 | 1 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.120s | 1.063ms | 6 | 6 | 100.00 |
| i2c_host_fifo_fmt_empty | 2.990s | 1.454ms | 1 | 1 | 100.00 | ||
| i2c_host_fifo_reset_rx | 3.460s | 974.523us | 3 | 3 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 38.030s | 10.674ms | 1 | 1 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 21.930s | 9.248ms | 1 | 1 | 100.00 |
| V2 | host_rx_oversample | host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 2.090s | 158.658us | 3 | 5 | 60.00 |
| V2 | target_glitch | i2c_target_glitch | 2.800s | 646.222us | 0 | 2 | 0.00 |
| V2 | target_stress_all | i2c_target_stress_all | 19.085m | 47.630ms | 4 | 4 | 100.00 |
| V2 | target_maxperf | i2c_target_perf | 3.590s | 1.598ms | 1 | 1 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 23.330s | 1.013ms | 3 | 3 | 100.00 |
| i2c_target_intr_smoke | 4.080s | 15.470ms | 1 | 1 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 1.760s | 446.621us | 5 | 5 | 100.00 |
| i2c_target_fifo_reset_tx | 0.960s | 963.187us | 1 | 1 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 2.874m | 29.149ms | 4 | 4 | 100.00 |
| i2c_target_stress_rd | 23.330s | 1.013ms | 3 | 3 | 100.00 | ||
| i2c_target_intr_stress_wr | 4.678m | 15.872ms | 4 | 4 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 4.960s | 7.727ms | 1 | 1 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 1.900s | 1.992ms | 1 | 1 | 100.00 |
| V2 | bad_address | i2c_target_bad_addr | 4.470s | 970.547us | 4 | 4 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 1.470s | 740.462us | 3 | 3 | 100.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 1.690s | 601.569us | 1 | 1 | 100.00 |
| i2c_target_fifo_watermarks_tx | 1.000s | 130.334us | 1 | 1 | 100.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 5.625m | 12.281ms | 5 | 5 | 100.00 |
| i2c_host_perf_precise | 0.890s | 192.214us | 1 | 1 | 100.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 21.930s | 9.248ms | 1 | 1 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 3.150s | 271.953us | 1 | 1 | 100.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 2.770s | 607.312us | 4 | 4 | 100.00 |
| i2c_target_nack_acqfull_addr | 2.280s | 849.739us | 5 | 5 | 100.00 | ||
| i2c_target_nack_txstretch | 1.440s | 137.162us | 3 | 3 | 100.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 14.550s | 1.084ms | 8 | 8 | 100.00 |
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 1.800s | 1.092ms | 1 | 1 | 100.00 |
| V2 | alert_test | i2c_alert_test | 0.670s | 38.814us | 3 | 3 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.510s | 21.701us | 6 | 6 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 1.470s | 125.621us | 4 | 4 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 1.470s | 125.621us | 4 | 4 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.560s | 24.929us | 3 | 3 | 100.00 |
| i2c_csr_rw | 0.620s | 193.436us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.030s | 44.816us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 0.710s | 49.187us | 4 | 4 | 100.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.560s | 24.929us | 3 | 3 | 100.00 |
| i2c_csr_rw | 0.620s | 193.436us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.030s | 44.816us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 0.710s | 49.187us | 4 | 4 | 100.00 | ||
| V2 | TOTAL | 107 | 117 | 91.45 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 1.230s | 131.758us | 8 | 8 | 100.00 |
| i2c_sec_cm | 0.940s | 74.033us | 3 | 3 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 1.230s | 131.758us | 8 | 8 | 100.00 |
| V2S | TOTAL | 11 | 11 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 31.800s | 2.022ms | 0 | 10 | 0.00 |
| V3 | target_error_intr | i2c_target_unexp_stop | 1.050s | 84.228us | 0 | 1 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 23.430s | 2.108ms | 0 | 10 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 21 | 0.00 | |||
| TOTAL | 177 | 208 | 85.10 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 7 | 100.00 |
| V2 | 49 | 38 | 34 | 69.39 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 4 | 3 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 86.26 | 97.25 | 89.18 | 89.66 | 47.62 | 93.83 | 96.41 | 89.85 |
UVM_ERROR (cip_base_vseq.sv:1237) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 16 failures:
0.i2c_host_stress_all_with_rand_reset.12354840518228006670111121645055193910297605210676044605011955795990753023352
Line 95, in log /home/runner/_work/pavona/pavona/scratch/main/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4015116453 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4015116453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.35198402379871812055773235241799764399701958399670668138511354171383210921855
Line 117, in log /home/runner/_work/pavona/pavona/scratch/main/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2021540328 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2021540328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
0.i2c_target_stress_all_with_rand_reset.108339759948209762281119320346158077440616653578812014210009864352109594764863
Line 94, in log /home/runner/_work/pavona/pavona/scratch/main/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 936576776 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 936576776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_stress_all_with_rand_reset.115616222974382729827949116860117593035156932901145443854048384811474885338095
Line 90, in log /home/runner/_work/pavona/pavona/scratch/main/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 171379041 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 171379041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 7 failures:
2.i2c_host_error_intr.90166329408195431271864370015799979022659222804039058847461120026540357439480
Line 101, in log /home/runner/_work/pavona/pavona/scratch/main/i2c-sim-vcs/2.i2c_host_error_intr/latest/run.log
UVM_ERROR @ 19833853 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 19833853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_host_error_intr.31876555143624209290925397485294450091377753462533235634679036517564291234828
Line 149, in log /home/runner/_work/pavona/pavona/scratch/main/i2c-sim-vcs/3.i2c_host_error_intr/latest/run.log
UVM_ERROR @ 63710917 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 63710917 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
3.i2c_target_stress_all_with_rand_reset.5501634010157488099679181206324059738909748361834229463663786985396166176764
Line 88, in log /home/runner/_work/pavona/pavona/scratch/main/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 74131425 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 74131425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_stress_all_with_rand_reset.6508172269535680365981979940086467265462186805537740467963225433159163371644
Line 92, in log /home/runner/_work/pavona/pavona/scratch/main/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 10123025 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 10123025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
5.i2c_host_stress_all.76931573866213829031058073930059198354720725295007177002398593419110478224206
Line 186, in log /home/runner/_work/pavona/pavona/scratch/main/i2c-sim-vcs/5.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 205471098392 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 205471098392 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 3 failures:
Test i2c_host_mode_toggle has 1 failures.
3.i2c_host_mode_toggle.79985590844386067273893734463771098061732996069977586466532877622653784478123
Line 92, in log /home/runner/_work/pavona/pavona/scratch/main/i2c-sim-vcs/3.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 162585382 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @22295
Test i2c_host_stress_all has 2 failures.
4.i2c_host_stress_all.90922633213476056860941202734996100349215202952218306778822672203301071167840
Line 159, in log /home/runner/_work/pavona/pavona/scratch/main/i2c-sim-vcs/4.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 20971298517 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @16619628
6.i2c_host_stress_all.41341070549530758453639035882966397221440466141411848216972345567303923032293
Line 167, in log /home/runner/_work/pavona/pavona/scratch/main/i2c-sim-vcs/6.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 42234810792 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @3196142
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 2 failures:
0.i2c_target_glitch.42764473122436264332061872710055767260821554613301755592101770623118047995239
Line 91, in log /home/runner/_work/pavona/pavona/scratch/main/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log
UVM_ERROR @ 646222475 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
UVM_INFO @ 646222475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_glitch.99295224833206251578599809374694659852186196614041213005979721162085209162878
Line 86, in log /home/runner/_work/pavona/pavona/scratch/main/i2c-sim-vcs/1.i2c_target_glitch/latest/run.log
UVM_ERROR @ 438976970 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
UVM_INFO @ 438976970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:
0.i2c_target_unexp_stop.82751664746363375126798017885367838880802735430307758802994941239139981759879
Line 85, in log /home/runner/_work/pavona/pavona/scratch/main/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 84227702 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 236 [0xec])
UVM_INFO @ 84227702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1150) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
4.i2c_target_stress_all_with_rand_reset.15082565012467298559661901211213895125385366857964041114748758694381458492644
Line 101, in log /home/runner/_work/pavona/pavona/scratch/main/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2107978860 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 2107978860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 1 failures:
4.i2c_host_mode_toggle.26358307898979209193655074887492735184231768769597927072774704969105827022354
Line 94, in log /home/runner/_work/pavona/pavona/scratch/main/i2c-sim-vcs/4.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 181309878 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------