KEYMGR Simulation Results

Saturday June 06 2026 03:15:30 UTC

GitHub Revision: 285e653a0b

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	2.020s	83.577us	1	1	100.00
V1	random	keymgr_random	3.370s	404.160us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.270s	25.168us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.200s	45.447us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	13.470s	646.767us	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	8.380s	1.639ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	1.550s	356.743us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.200s	45.447us	20	20	100.00
		keymgr_csr_aliasing	8.380s	1.639ms	5	5	100.00
V1		TOTAL			57	57	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	1.136m	14.470ms	24	24	100.00
V2	sideload	keymgr_sideload	13.300s	1.295ms	3	3	100.00
		keymgr_sideload_kmac	27.310s	13.802ms	3	3	100.00
		keymgr_sideload_aes	2.330s	190.901us	1	1	100.00
		keymgr_sideload_acc	2.310s	180.325us	3	3	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	0.840s	83.065us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	3.400s	476.789us	8	8	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	3.670s	213.743us	13	14	92.86
V2	invalid_sw_input	keymgr_sw_invalid_input	4.770s	144.487us	6	6	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	26.580s	12.199ms	13	13	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	3.380s	551.261us	4	4	100.00
V2	stress_all	keymgr_stress_all	3.402m	146.709ms	24	24	100.00
V2	intr_test	keymgr_intr_test	0.950s	44.344us	50	50	100.00
V2	alert_test	keymgr_alert_test	0.900s	39.006us	3	3	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	3.850s	594.946us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	3.850s	594.946us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.270s	25.168us	5	5	100.00
		keymgr_csr_rw	1.200s	45.447us	20	20	100.00
		keymgr_csr_aliasing	8.380s	1.639ms	5	5	100.00
		keymgr_same_csr_outstanding	2.810s	80.132us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.270s	25.168us	5	5	100.00
		keymgr_csr_rw	1.200s	45.447us	20	20	100.00
		keymgr_csr_aliasing	8.380s	1.639ms	5	5	100.00
		keymgr_same_csr_outstanding	2.810s	80.132us	20	20	100.00
V2		TOTAL			196	197	99.49
V2S	sec_cm_additional_check	keymgr_sec_cm	9.300s	1.586ms	3	3	100.00
V2S	tl_intg_err	keymgr_sec_cm	9.300s	1.586ms	3	3	100.00
		keymgr_tl_intg_err	9.270s	520.258us	21	21	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	2.580s	92.228us	3	3	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	2.580s	92.228us	3	3	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	2.580s	92.228us	3	3	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	2.580s	92.228us	3	3	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	9.860s	438.539us	3	3	100.00
V2S	prim_count_check	keymgr_sec_cm	9.300s	1.586ms	3	3	100.00
V2S	prim_fsm_check	keymgr_sec_cm	9.300s	1.586ms	3	3	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	9.270s	520.258us	21	21	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	2.580s	92.228us	3	3	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.136m	14.470ms	24	24	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	3.370s	404.160us	1	1	100.00
		keymgr_csr_rw	1.200s	45.447us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	3.370s	404.160us	1	1	100.00
		keymgr_csr_rw	1.200s	45.447us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	3.370s	404.160us	1	1	100.00
		keymgr_csr_rw	1.200s	45.447us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	3.400s	476.789us	8	8	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	26.580s	12.199ms	13	13	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	26.580s	12.199ms	13	13	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	3.370s	404.160us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	2.360s	484.643us	4	4	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	9.300s	1.586ms	3	3	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	9.300s	1.586ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	9.300s	1.586ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	3.390s	123.914us	30	30	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	3.400s	476.789us	8	8	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	9.300s	1.586ms	3	3	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	9.300s	1.586ms	3	3	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	9.300s	1.586ms	3	3	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	3.390s	123.914us	30	30	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	3.390s	123.914us	30	30	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	9.300s	1.586ms	3	3	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	3.390s	123.914us	30	30	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	9.300s	1.586ms	3	3	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	3.390s	123.914us	30	30	100.00
V2S		TOTAL			64	64	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	13.810s	933.236us	8	11	72.73
V3		TOTAL			8	11	72.73
		TOTAL			325	329	98.78

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	16	16	15	93.75
V2S	6	6	6	100.00
V3	1	1	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.64	99.21	98.30	98.00	100.00	99.01	97.72	91.21

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:1237) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
  • Test keymgr_stress_all_with_rand_reset has 3 failures.

    • 6.keymgr_stress_all_with_rand_reset.59098054605818472416598527118894687985524202011339631022504442436424087865529
      Line 336, in log /home/runner/_work/pavona/pavona/scratch/main/keymgr-sim-vcs/6.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 178693671 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 178693671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 7.keymgr_stress_all_with_rand_reset.22114590639649120715173035708814909951100543678364834276689668101186584235833
      Line 145, in log /home/runner/_work/pavona/pavona/scratch/main/keymgr-sim-vcs/7.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 113472017 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 113472017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:267) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_operation_err triggered unexpectedly has 1 failures:
  • Test keymgr_kmac_rsp_err has 1 failures.

    • 12.keymgr_kmac_rsp_err.48289694206428447639599962926109968774927635762298110696661946198102972545630
      Line 311, in log /home/runner/_work/pavona/pavona/scratch/main/keymgr-sim-vcs/12.keymgr_kmac_rsp_err/latest/run.log

        UVM_ERROR @  64048504 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_operation_err triggered unexpectedly
        UVM_INFO @  64048504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---