KEYMGR_DPE Simulation Results

Saturday June 06 2026 03:15:30 UTC

GitHub Revision: 285e653a0b

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_dpe_smoke	6.329m	123.992ms	31	31	100.00
V1	csr_hw_reset	keymgr_dpe_csr_hw_reset	1.250s	34.181us	5	5	100.00
V1	csr_rw	keymgr_dpe_csr_rw	1.310s	233.297us	20	20	100.00
V1	csr_bit_bash	keymgr_dpe_csr_bit_bash	10.720s	712.455us	5	5	100.00
V1	csr_aliasing	keymgr_dpe_csr_aliasing	3.810s	875.421us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_dpe_csr_mem_rw_with_rand_reset	1.830s	96.068us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_dpe_csr_rw	1.310s	233.297us	20	20	100.00
		keymgr_dpe_csr_aliasing	3.810s	875.421us	5	5	100.00
V1		TOTAL			86	86	100.00
V2	intr_test	keymgr_dpe_intr_test	0.800s	17.141us	5	5	100.00
V2	alert_test	keymgr_dpe_alert_test	0.860s	30.783us	3	3	100.00
V2	tl_d_oob_addr_access	keymgr_dpe_tl_errors	2.750s	384.566us	5	5	100.00
V2	tl_d_illegal_access	keymgr_dpe_tl_errors	2.750s	384.566us	5	5	100.00
V2	tl_d_outstanding_access	keymgr_dpe_csr_hw_reset	1.250s	34.181us	5	5	100.00
		keymgr_dpe_csr_rw	1.310s	233.297us	20	20	100.00
		keymgr_dpe_csr_aliasing	3.810s	875.421us	5	5	100.00
		keymgr_dpe_same_csr_outstanding	2.080s	85.425us	3	3	100.00
V2	tl_d_partial_access	keymgr_dpe_csr_hw_reset	1.250s	34.181us	5	5	100.00
		keymgr_dpe_csr_rw	1.310s	233.297us	20	20	100.00
		keymgr_dpe_csr_aliasing	3.810s	875.421us	5	5	100.00
		keymgr_dpe_same_csr_outstanding	2.080s	85.425us	3	3	100.00
V2		TOTAL			16	16	100.00
V2S	tl_intg_err	keymgr_dpe_sec_cm	10.860s	657.662us	5	5	100.00
		keymgr_dpe_tl_intg_err	5.340s	234.362us	15	15	100.00
V2S	shadow_reg_update_error	keymgr_dpe_shadow_reg_errors	2.130s	475.961us	4	4	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_dpe_shadow_reg_errors	2.130s	475.961us	4	4	100.00
V2S	shadow_reg_storage_error	keymgr_dpe_shadow_reg_errors	2.130s	475.961us	4	4	100.00
V2S	shadowed_reset_glitch	keymgr_dpe_shadow_reg_errors	2.130s	475.961us	4	4	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_dpe_shadow_reg_errors_with_csr_rw	3.380s	572.836us	4	4	100.00
V2S	prim_count_check	keymgr_dpe_sec_cm	10.860s	657.662us	5	5	100.00
V2S	prim_fsm_check	keymgr_dpe_sec_cm	10.860s	657.662us	5	5	100.00
V2S		TOTAL			28	28	100.00
V3	stress_all_with_rand_reset	keymgr_dpe_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			130	130	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	4	4	4	100.00
V2S	4	4	4	100.00
V3	1	0	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
76.53	97.70	90.35	62.37	75.68	94.61	97.64	17.36