KMAC/MASKED Simulation Results

Saturday June 06 2026 03:15:30 UTC

GitHub Revision: 285e653a0b

Branch: main

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke kmac_smoke 56.120s 8.219ms 3 3 100.00
V1 csr_hw_reset kmac_csr_hw_reset 1.200s 54.338us 5 5 100.00
V1 csr_rw kmac_csr_rw 1.260s 31.645us 20 20 100.00
V1 csr_bit_bash kmac_csr_bit_bash 11.700s 991.016us 3 3 100.00
V1 csr_aliasing kmac_csr_aliasing 7.750s 383.568us 5 5 100.00
V1 csr_mem_rw_with_rand_reset kmac_csr_mem_rw_with_rand_reset 2.250s 34.657us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr kmac_csr_rw 1.260s 31.645us 20 20 100.00
kmac_csr_aliasing 7.750s 383.568us 5 5 100.00
V1 mem_walk kmac_mem_walk 0.870s 45.386us 5 5 100.00
V1 mem_partial_access kmac_mem_partial_access 1.590s 134.650us 5 5 100.00
V1 TOTAL 66 66 100.00
V2 long_msg_and_output kmac_long_msg_and_output 32.041m 141.257ms 1 1 100.00
V2 burst_write kmac_burst_write 9.703m 17.228ms 1 1 100.00
V2 test_vectors kmac_test_vectors_sha3_224 27.207m 304.514ms 5 5 100.00
kmac_test_vectors_sha3_256 23.695m 56.386ms 3 3 100.00
kmac_test_vectors_sha3_384 20.248m 45.833ms 5 5 100.00
kmac_test_vectors_sha3_512 12.031m 13.060ms 3 3 100.00
kmac_test_vectors_shake_128 33.797m 148.367ms 5 5 100.00
kmac_test_vectors_shake_256 28.390m 89.757ms 5 5 100.00
kmac_test_vectors_kmac 2.780s 310.151us 5 5 100.00
kmac_test_vectors_kmac_xof 2.630s 45.543us 5 5 100.00
V2 sideload kmac_sideload 5.339m 5.740ms 3 3 100.00
V2 app kmac_app 4.589m 49.582ms 1 1 100.00
V2 app_with_partial_data kmac_app_with_partial_data 3.001m 32.422ms 3 3 100.00
V2 entropy_refresh kmac_entropy_refresh 3.177m 26.113ms 7 7 100.00
V2 error kmac_error 5.583m 112.925ms 5 5 100.00
V2 key_error kmac_key_error 10.270s 6.431ms 3 3 100.00
V2 sideload_invalid kmac_sideload_invalid 7.860s 4.398ms 5 5 100.00
V2 edn_timeout_error kmac_edn_timeout_error 17.720s 3.124ms 3 3 100.00
V2 entropy_mode_error kmac_entropy_mode_error 1.010s 85.280us 3 3 100.00
V2 entropy_ready_error kmac_entropy_ready_error 35.660s 24.489ms 3 3 100.00
V2 lc_escalation kmac_lc_escalation 21.910s 4.068ms 14 14 100.00
V2 stress_all kmac_stress_all 11.557m 37.676ms 4 4 100.00
V2 intr_test kmac_intr_test 0.910s 52.664us 5 5 100.00
V2 alert_test kmac_alert_test 0.910s 66.963us 3 3 100.00
V2 tl_d_oob_addr_access kmac_tl_errors 3.680s 175.081us 20 20 100.00
V2 tl_d_illegal_access kmac_tl_errors 3.680s 175.081us 20 20 100.00
V2 tl_d_outstanding_access kmac_csr_hw_reset 1.200s 54.338us 5 5 100.00
kmac_csr_rw 1.260s 31.645us 20 20 100.00
kmac_csr_aliasing 7.750s 383.568us 5 5 100.00
kmac_same_csr_outstanding 2.540s 678.671us 20 20 100.00
V2 tl_d_partial_access kmac_csr_hw_reset 1.200s 54.338us 5 5 100.00
kmac_csr_rw 1.260s 31.645us 20 20 100.00
kmac_csr_aliasing 7.750s 383.568us 5 5 100.00
kmac_same_csr_outstanding 2.540s 678.671us 20 20 100.00
V2 TOTAL 140 140 100.00
V2S shadow_reg_update_error kmac_shadow_reg_errors 2.130s 96.638us 3 3 100.00
V2S shadow_reg_read_clear_staged_value kmac_shadow_reg_errors 2.130s 96.638us 3 3 100.00
V2S shadow_reg_storage_error kmac_shadow_reg_errors 2.130s 96.638us 3 3 100.00
V2S shadowed_reset_glitch kmac_shadow_reg_errors 2.130s 96.638us 3 3 100.00
V2S shadow_reg_update_error_with_csr_rw kmac_shadow_reg_errors_with_csr_rw 4.930s 961.495us 3 3 100.00
V2S tl_intg_err kmac_sec_cm 58.170s 6.727ms 4 4 100.00
kmac_tl_intg_err 4.590s 903.253us 7 7 100.00
V2S sec_cm_bus_integrity kmac_tl_intg_err 4.590s 903.253us 7 7 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi kmac_lc_escalation 21.910s 4.068ms 14 14 100.00
V2S sec_cm_sw_key_key_masking kmac_smoke 56.120s 8.219ms 3 3 100.00
V2S sec_cm_key_sideload kmac_sideload 5.339m 5.740ms 3 3 100.00
V2S sec_cm_cfg_shadowed_config_shadow kmac_shadow_reg_errors 2.130s 96.638us 3 3 100.00
V2S sec_cm_fsm_sparse kmac_sec_cm 58.170s 6.727ms 4 4 100.00
V2S sec_cm_ctr_redun kmac_sec_cm 58.170s 6.727ms 4 4 100.00
V2S sec_cm_packer_ctr_redun kmac_sec_cm 58.170s 6.727ms 4 4 100.00
V2S sec_cm_cfg_shadowed_config_regwen kmac_smoke 56.120s 8.219ms 3 3 100.00
V2S sec_cm_fsm_global_esc kmac_lc_escalation 21.910s 4.068ms 14 14 100.00
V2S sec_cm_fsm_local_esc kmac_sec_cm 58.170s 6.727ms 4 4 100.00
V2S sec_cm_absorbed_ctrl_mubi kmac_mubi 4.310m 5.856ms 3 3 100.00
V2S sec_cm_sw_cmd_ctrl_sparse kmac_smoke 56.120s 8.219ms 3 3 100.00
V2S TOTAL 20 20 100.00
V3 throughput kmac_throughput 0 0 --
V3 stress_all_with_rand_reset kmac_stress_all_with_rand_reset 2.298m 4.235ms 5 5 100.00
V3 TOTAL 5 5 100.00
TOTAL 231 231 100.00

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 26 26 26 100.00
V2S 5 5 5 100.00
V3 2 1 1 50.00

Coverage Results

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
93.78 99.10 94.14 95.53 76.13 96.31 97.74 97.52