KMAC/UNMASKED Simulation Results

Saturday June 06 2026 03:15:30 UTC

GitHub Revision: 285e653a0b

Branch: main

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke kmac_smoke 30.960s 829.807us 1 1 100.00
V1 csr_hw_reset kmac_csr_hw_reset 0.920s 26.040us 5 5 100.00
V1 csr_rw kmac_csr_rw 1.090s 18.970us 20 20 100.00
V1 csr_bit_bash kmac_csr_bit_bash 12.080s 1.497ms 5 5 100.00
V1 csr_aliasing kmac_csr_aliasing 5.470s 402.707us 5 5 100.00
V1 csr_mem_rw_with_rand_reset kmac_csr_mem_rw_with_rand_reset 2.430s 178.491us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr kmac_csr_rw 1.090s 18.970us 20 20 100.00
kmac_csr_aliasing 5.470s 402.707us 5 5 100.00
V1 mem_walk kmac_mem_walk 0.860s 15.958us 5 5 100.00
V1 mem_partial_access kmac_mem_partial_access 1.180s 54.571us 5 5 100.00
V1 TOTAL 66 66 100.00
V2 long_msg_and_output kmac_long_msg_and_output 44.819m 485.188ms 1 1 100.00
V2 burst_write kmac_burst_write 4.748m 14.066ms 3 3 100.00
V2 test_vectors kmac_test_vectors_sha3_224 24.788m 195.350ms 5 5 100.00
kmac_test_vectors_sha3_256 27.013m 365.092ms 5 5 100.00
kmac_test_vectors_sha3_384 17.016m 87.033ms 5 5 100.00
kmac_test_vectors_sha3_512 14.149m 283.795ms 5 5 100.00
kmac_test_vectors_shake_128 32.814m 72.996ms 5 5 100.00
kmac_test_vectors_shake_256 3.819m 91.163ms 3 3 100.00
kmac_test_vectors_kmac 1.960s 151.195us 5 5 100.00
kmac_test_vectors_kmac_xof 2.600s 116.193us 5 5 100.00
V2 sideload kmac_sideload 4.575m 67.066ms 1 1 100.00
V2 app kmac_app 2.844m 13.221ms 4 4 100.00
V2 app_with_partial_data kmac_app_with_partial_data 3.870m 17.406ms 10 10 100.00
V2 entropy_refresh kmac_entropy_refresh 3.837m 15.925ms 4 4 100.00
V2 error kmac_error 3.170m 32.645ms 6 6 100.00
V2 key_error kmac_key_error 6.640s 10.951ms 3 3 100.00
V2 sideload_invalid kmac_sideload_invalid 3.930s 2.101ms 5 5 100.00
V2 edn_timeout_error kmac_edn_timeout_error 29.580s 5.952ms 20 20 100.00
V2 entropy_mode_error kmac_entropy_mode_error 28.390s 7.164ms 20 20 100.00
V2 entropy_ready_error kmac_entropy_ready_error 36.690s 6.859ms 3 3 100.00
V2 lc_escalation kmac_lc_escalation 30.290s 1.245ms 11 11 100.00
V2 stress_all kmac_stress_all 17.198m 122.524ms 6 6 100.00
V2 intr_test kmac_intr_test 0.890s 19.475us 5 5 100.00
V2 alert_test kmac_alert_test 1.000s 367.346us 3 3 100.00
V2 tl_d_oob_addr_access kmac_tl_errors 2.630s 126.955us 20 20 100.00
V2 tl_d_illegal_access kmac_tl_errors 2.630s 126.955us 20 20 100.00
V2 tl_d_outstanding_access kmac_csr_hw_reset 0.920s 26.040us 5 5 100.00
kmac_csr_rw 1.090s 18.970us 20 20 100.00
kmac_csr_aliasing 5.470s 402.707us 5 5 100.00
kmac_same_csr_outstanding 2.390s 92.332us 20 20 100.00
V2 tl_d_partial_access kmac_csr_hw_reset 0.920s 26.040us 5 5 100.00
kmac_csr_rw 1.090s 18.970us 20 20 100.00
kmac_csr_aliasing 5.470s 402.707us 5 5 100.00
kmac_same_csr_outstanding 2.390s 92.332us 20 20 100.00
V2 TOTAL 183 183 100.00
V2S shadow_reg_update_error kmac_shadow_reg_errors 1.910s 84.911us 4 4 100.00
V2S shadow_reg_read_clear_staged_value kmac_shadow_reg_errors 1.910s 84.911us 4 4 100.00
V2S shadow_reg_storage_error kmac_shadow_reg_errors 1.910s 84.911us 4 4 100.00
V2S shadowed_reset_glitch kmac_shadow_reg_errors 1.910s 84.911us 4 4 100.00
V2S shadow_reg_update_error_with_csr_rw kmac_shadow_reg_errors_with_csr_rw 3.750s 200.531us 3 3 100.00
V2S tl_intg_err kmac_sec_cm 50.700s 19.443ms 3 3 100.00
kmac_tl_intg_err 3.610s 1.840ms 7 7 100.00
V2S sec_cm_bus_integrity kmac_tl_intg_err 3.610s 1.840ms 7 7 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi kmac_lc_escalation 30.290s 1.245ms 11 11 100.00
V2S sec_cm_sw_key_key_masking kmac_smoke 30.960s 829.807us 1 1 100.00
V2S sec_cm_key_sideload kmac_sideload 4.575m 67.066ms 1 1 100.00
V2S sec_cm_cfg_shadowed_config_shadow kmac_shadow_reg_errors 1.910s 84.911us 4 4 100.00
V2S sec_cm_fsm_sparse kmac_sec_cm 50.700s 19.443ms 3 3 100.00
V2S sec_cm_ctr_redun kmac_sec_cm 50.700s 19.443ms 3 3 100.00
V2S sec_cm_packer_ctr_redun kmac_sec_cm 50.700s 19.443ms 3 3 100.00
V2S sec_cm_cfg_shadowed_config_regwen kmac_smoke 30.960s 829.807us 1 1 100.00
V2S sec_cm_fsm_global_esc kmac_lc_escalation 30.290s 1.245ms 11 11 100.00
V2S sec_cm_fsm_local_esc kmac_sec_cm 50.700s 19.443ms 3 3 100.00
V2S sec_cm_absorbed_ctrl_mubi kmac_mubi 3.868m 17.573ms 3 3 100.00
V2S sec_cm_sw_cmd_ctrl_sparse kmac_smoke 30.960s 829.807us 1 1 100.00
V2S TOTAL 20 20 100.00
V3 throughput kmac_throughput 0 0 --
V3 stress_all_with_rand_reset kmac_stress_all_with_rand_reset 1.370m 8.432ms 3 3 100.00
V3 TOTAL 3 3 100.00
TOTAL 272 272 100.00

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 26 26 26 100.00
V2S 5 5 5 100.00
V3 2 1 1 50.00

Coverage Results

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
93.12 97.56 94.08 99.78 71.64 95.12 97.56 96.11