LC_CTRL/DMI_VOLATILE_UNLOCK_DISABLED Simulation Results

Saturday June 06 2026 03:15:30 UTC

GitHub Revision: 285e653a0b

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	5.180s	176.372us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	0.890s	18.384us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	0.760s	43.259us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.680s	93.174us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.130s	41.991us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.270s	24.262us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	0.760s	43.259us	20	20	100.00
		lc_ctrl_csr_aliasing	1.130s	41.991us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	5.950s	335.106us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	10.110s	277.332us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.000s	20.480us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	2.860s	484.080us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	10.030s	2.690ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	10.700s	3.885ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	10.030s	2.690ms	50	50	100.00
		lc_ctrl_prog_failure	2.860s	484.080us	50	50	100.00
		lc_ctrl_errors	10.700s	3.885ms	50	50	100.00
		lc_ctrl_security_escalation	8.520s	668.793us	50	50	100.00
		lc_ctrl_jtag_state_failure	52.530s	3.086ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	11.130s	505.276us	20	20	100.00
		lc_ctrl_jtag_errors	1.236m	84.722ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	8.230s	3.203ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	21.040s	1.075ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	11.130s	505.276us	20	20	100.00
		lc_ctrl_jtag_errors	1.236m	84.722ms	20	20	100.00
		lc_ctrl_jtag_access	13.540s	1.131ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	22.960s	4.199ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	2.560s	321.579us	10	10	100.00
		lc_ctrl_jtag_csr_rw	1.190s	364.630us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	16.280s	1.358ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	8.070s	3.304ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	0.980s	22.464us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	2.300s	505.486us	10	10	100.00
		lc_ctrl_jtag_alert_test	1.150s	267.307us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	15.560s	4.862ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.110s	17.862us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	6.058m	15.021ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.440s	40.611us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	3.020s	276.481us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	3.020s	276.481us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	0.890s	18.384us	5	5	100.00
		lc_ctrl_csr_rw	0.760s	43.259us	20	20	100.00
		lc_ctrl_csr_aliasing	1.130s	41.991us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.180s	50.974us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	0.890s	18.384us	5	5	100.00
		lc_ctrl_csr_rw	0.760s	43.259us	20	20	100.00
		lc_ctrl_csr_aliasing	1.130s	41.991us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.180s	50.974us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	6.610s	620.853us	5	5	100.00
		lc_ctrl_tl_intg_err	2.110s	486.519us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	2.110s	486.519us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	10.110s	277.332us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	10.030s	2.690ms	50	50	100.00
		lc_ctrl_sec_cm	6.610s	620.853us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	10.030s	2.690ms	50	50	100.00
		lc_ctrl_sec_cm	6.610s	620.853us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	10.030s	2.690ms	50	50	100.00
		lc_ctrl_sec_cm	6.610s	620.853us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	10.030s	2.690ms	50	50	100.00
		lc_ctrl_sec_cm	6.610s	620.853us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	10.030s	2.690ms	50	50	100.00
		lc_ctrl_sec_cm	6.610s	620.853us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	10.030s	2.690ms	50	50	100.00
		lc_ctrl_sec_cm	6.610s	620.853us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	10.030s	2.690ms	50	50	100.00
		lc_ctrl_sec_cm	6.610s	620.853us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	10.030s	2.690ms	50	50	100.00
		lc_ctrl_sec_cm	6.610s	620.853us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	8.520s	668.793us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	5.950s	335.106us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	21.040s	1.075ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	12.840s	2.344ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	12.840s	2.344ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	10.750s	1.137ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	11.460s	686.920us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	11.460s	686.920us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.311m	13.008ms	18	50	36.00
V3		TOTAL			18	50	36.00
		TOTAL			997	1030	96.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.25	97.90	82.79	90.03	100.00	96.99	95.99	96.04

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:1237) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 25 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 25 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.4519171571944342931326306341387060597366480991448878487490196509576877723683
      Line 3016, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_dmi_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2918713145 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2918713145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.lc_ctrl_stress_all_with_rand_reset.115295550294177230138516886899359091230880009147186749777753434284261432994509
      Line 592, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_dmi_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 817922418 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 817922418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 23 more failures.

• UVM_ERROR (cip_base_vseq.sv:912) virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error has 5 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 5 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.46203593575931730333590026636878693574628660906221191003774472577660843438895
      Line 12633, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_dmi_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3946725771 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
        UVM_INFO @ 3946725771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 25.lc_ctrl_stress_all_with_rand_reset.23449498604799771953299804793590897731210131001809285118655865633167066677653
      Line 2198, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_dmi_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1931246123 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
        UVM_INFO @ 1931246123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 3 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 2 failures:

  • Test lc_ctrl_stress_all has 1 failures.

    • 11.lc_ctrl_stress_all.3053082897983792575984810294572752798723076376072053067692538515197211642869
      Line 7638, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_dmi_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 11585559160 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 11585559160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 22.lc_ctrl_stress_all_with_rand_reset.62400798819184565402217712457716667365278647876063152234083136132370830885224
      Line 4048, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_dmi_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1816136418 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 1816136418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1150) [lc_ctrl_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 38.lc_ctrl_stress_all_with_rand_reset.52898207974282102278124255632954287460623751254166098869172001224428181102631
      Line 1236, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_dmi_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1840394329 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 1840394329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---