LC_CTRL/DMI_VOLATILE_UNLOCK_ENABLED Simulation Results

Saturday June 06 2026 03:15:30 UTC

GitHub Revision: 285e653a0b

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	5.280s	672.463us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	0.830s	69.420us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	0.900s	48.083us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.670s	1.722ms	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.010s	41.755us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.150s	116.329us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	0.900s	48.083us	20	20	100.00
		lc_ctrl_csr_aliasing	1.010s	41.755us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	6.140s	744.314us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	8.750s	1.864ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.930s	14.618us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	3.810s	517.078us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	11.290s	1.619ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	11.250s	2.505ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	11.290s	1.619ms	50	50	100.00
		lc_ctrl_prog_failure	3.810s	517.078us	50	50	100.00
		lc_ctrl_errors	11.250s	2.505ms	50	50	100.00
		lc_ctrl_security_escalation	7.680s	3.036ms	50	50	100.00
		lc_ctrl_jtag_state_failure	51.180s	12.937ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	16.970s	2.601ms	20	20	100.00
		lc_ctrl_jtag_errors	48.980s	8.854ms	19	20	95.00
V2	jtag_access	lc_ctrl_jtag_smoke	6.640s	448.070us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	19.370s	4.763ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	16.970s	2.601ms	20	20	100.00
		lc_ctrl_jtag_errors	48.980s	8.854ms	19	20	95.00
		lc_ctrl_jtag_access	13.620s	4.451ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	21.420s	1.319ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	2.630s	409.345us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.740s	798.655us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	12.390s	5.281ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	14.120s	1.426ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.060s	73.910us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	2.500s	173.457us	10	10	100.00
		lc_ctrl_jtag_alert_test	1.480s	90.375us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	5.610s	2.458ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.270s	61.896us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	6.648m	43.449ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.160s	22.735us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	3.400s	171.014us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	3.400s	171.014us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	0.830s	69.420us	5	5	100.00
		lc_ctrl_csr_rw	0.900s	48.083us	20	20	100.00
		lc_ctrl_csr_aliasing	1.010s	41.755us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.150s	145.991us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	0.830s	69.420us	5	5	100.00
		lc_ctrl_csr_rw	0.900s	48.083us	20	20	100.00
		lc_ctrl_csr_aliasing	1.010s	41.755us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.150s	145.991us	20	20	100.00
V2		TOTAL			698	700	99.71
V2S	tl_intg_err	lc_ctrl_sec_cm	6.150s	429.435us	5	5	100.00
		lc_ctrl_tl_intg_err	4.020s	327.822us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.020s	327.822us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	8.750s	1.864ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	11.290s	1.619ms	50	50	100.00
		lc_ctrl_sec_cm	6.150s	429.435us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	11.290s	1.619ms	50	50	100.00
		lc_ctrl_sec_cm	6.150s	429.435us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	11.290s	1.619ms	50	50	100.00
		lc_ctrl_sec_cm	6.150s	429.435us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	11.290s	1.619ms	50	50	100.00
		lc_ctrl_sec_cm	6.150s	429.435us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	11.290s	1.619ms	50	50	100.00
		lc_ctrl_sec_cm	6.150s	429.435us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	11.290s	1.619ms	50	50	100.00
		lc_ctrl_sec_cm	6.150s	429.435us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	11.290s	1.619ms	50	50	100.00
		lc_ctrl_sec_cm	6.150s	429.435us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	11.290s	1.619ms	50	50	100.00
		lc_ctrl_sec_cm	6.150s	429.435us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	7.680s	3.036ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	6.140s	744.314us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	19.370s	4.763ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	10.200s	552.082us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	10.200s	552.082us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	9.410s	2.419ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	7.930s	2.848ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	7.930s	2.848ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.372m	22.263ms	18	50	36.00
V3		TOTAL			18	50	36.00
		TOTAL			996	1030	96.70

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	25	92.59
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.29	97.87	82.67	90.03	100.00	97.06	95.99	96.40

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:1237) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 29 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 29 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.10259710318545929030258531740759193117072297270272964450523719798189894950179
      Line 3767, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_dmi_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3317135814 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3317135814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.lc_ctrl_stress_all_with_rand_reset.12133713457557735295127474379874106783470057646312231081833487339400325188045
      Line 10506, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_dmi_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4440885644 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 4440885644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 27 more failures.

• UVM_ERROR (cip_base_vseq.sv:912) virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error has 3 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 36.lc_ctrl_stress_all_with_rand_reset.42455716860625458793086002541820957206314191470221839201941484593365972651777
      Line 7040, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_dmi_volatile_unlock_enabled-sim-vcs/36.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2579242270 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
        UVM_INFO @ 2579242270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 46.lc_ctrl_stress_all_with_rand_reset.109868432970288744613514867161789186807976236058691654128315417125511746072115
      Line 8285, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_dmi_volatile_unlock_enabled-sim-vcs/46.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 23531974919 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
        UVM_INFO @ 23531974919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:769) [lc_ctrl_lc_errors_vseq] Check failed otp_error_act == otp_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_stress_all has 1 failures.

    • 5.lc_ctrl_stress_all.9427358259465943806973882743938063191467087053022746619514516869146667746138
      Line 2766, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_dmi_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 2990132927 ps: (lc_ctrl_errors_vseq.sv:769) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed otp_error_act == otp_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 2990132927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_jtag_errors has 1 failures.

    • 18.lc_ctrl_jtag_errors.57789179207492418805497119050268517023973968647168496117201907507834315976047
      Line 287, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_dmi_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_jtag_errors/latest/run.log

        UVM_ERROR @  71515435 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @  71515435 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---