LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Saturday June 06 2026 03:15:30 UTC

GitHub Revision: `285e653a0b`

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	6.580s	764.546us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	0.900s	18.234us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	0.830s	12.586us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.960s	310.522us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.080s	43.445us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.170s	37.030us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	0.830s	12.586us	20	20	100.00
		lc_ctrl_csr_aliasing	1.080s	43.445us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	6.360s	637.277us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	13.440s	715.972us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.960s	13.571us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	3.300s	92.762us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	11.970s	1.291ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	11.520s	2.358ms	46	50	92.00
V2	security_escalation	lc_ctrl_state_failure	11.970s	1.291ms	50	50	100.00
		lc_ctrl_prog_failure	3.300s	92.762us	50	50	100.00
		lc_ctrl_errors	11.520s	2.358ms	46	50	92.00
		lc_ctrl_security_escalation	7.660s	434.164us	50	50	100.00
		lc_ctrl_jtag_state_failure	37.590s	2.205ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	13.810s	916.709us	20	20	100.00
		lc_ctrl_jtag_errors	46.780s	3.110ms	19	20	95.00
V2	jtag_access	lc_ctrl_jtag_smoke	7.160s	1.622ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	14.800s	882.552us	20	20	100.00
		lc_ctrl_jtag_prog_failure	13.810s	916.709us	20	20	100.00
		lc_ctrl_jtag_errors	46.780s	3.110ms	19	20	95.00
		lc_ctrl_jtag_access	14.820s	1.140ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	16.310s	1.128ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	1.900s	66.251us	10	10	100.00
		lc_ctrl_jtag_csr_rw	1.470s	435.961us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	15.340s	5.103ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	8.210s	1.346ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.110s	174.860us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	2.230s	266.622us	10	10	100.00
		lc_ctrl_jtag_alert_test	1.950s	221.797us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	6.230s	1.578ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.170s	17.155us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	6.956m	73.565ms	47	50	94.00
V2	alert_test	lc_ctrl_alert_test	1.500s	63.465us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	2.360s	224.302us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	2.360s	224.302us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	0.900s	18.234us	5	5	100.00
		lc_ctrl_csr_rw	0.830s	12.586us	20	20	100.00
		lc_ctrl_csr_aliasing	1.080s	43.445us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.190s	53.043us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	0.900s	18.234us	5	5	100.00
		lc_ctrl_csr_rw	0.830s	12.586us	20	20	100.00
		lc_ctrl_csr_aliasing	1.080s	43.445us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.190s	53.043us	20	20	100.00
V2		TOTAL			692	700	98.86
V2S	tl_intg_err	lc_ctrl_sec_cm	7.400s	374.346us	5	5	100.00
		lc_ctrl_tl_intg_err	1.860s	212.727us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	1.860s	212.727us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	13.440s	715.972us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	11.970s	1.291ms	50	50	100.00
		lc_ctrl_sec_cm	7.400s	374.346us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	11.970s	1.291ms	50	50	100.00
		lc_ctrl_sec_cm	7.400s	374.346us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	11.970s	1.291ms	50	50	100.00
		lc_ctrl_sec_cm	7.400s	374.346us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	11.970s	1.291ms	50	50	100.00
		lc_ctrl_sec_cm	7.400s	374.346us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	11.970s	1.291ms	50	50	100.00
		lc_ctrl_sec_cm	7.400s	374.346us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	11.970s	1.291ms	50	50	100.00
		lc_ctrl_sec_cm	7.400s	374.346us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	11.970s	1.291ms	50	50	100.00
		lc_ctrl_sec_cm	7.400s	374.346us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	11.970s	1.291ms	50	50	100.00
		lc_ctrl_sec_cm	7.400s	374.346us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	7.660s	434.164us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	6.360s	637.277us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	14.800s	882.552us	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	10.220s	875.943us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	10.220s	875.943us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	13.010s	22.071ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	9.170s	3.148ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	9.170s	3.148ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.380m	19.475ms	24	50	48.00
V3		TOTAL			24	50	48.00
		TOTAL			996	1030	96.70

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	24	88.89
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.94	97.26	81.92	88.25	77.66	94.27	94.13	96.09

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:1237) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 23 failures.
  - 1.lc_ctrl_stress_all_with_rand_reset.71560450718410826293292834850801982937956776502008810426604531351565608315635
    Line 809, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3150690798 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3150690798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.lc_ctrl_stress_all_with_rand_reset.68407271971815181805186439263535005929053811352161721179490775218109349492274
    Line 271, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 232069952 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 232069952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 21 more failures.

UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 9 failures:

Test lc_ctrl_errors has 4 failures.

0.lc_ctrl_errors.79703055184302697864602608882577191485155827726509733439847156468310952791986
Line 3680, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_errors/latest/run.log

  UVM_ERROR @ 567044242 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 567044242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

23.lc_ctrl_errors.67051676634503307830603762736038245665125266302584922024049390525411202270958
Line 2764, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_volatile_unlock_disabled-sim-vcs/23.lc_ctrl_errors/latest/run.log

  UVM_ERROR @ 1072626226 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1072626226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test lc_ctrl_stress_all has 3 failures.

1.lc_ctrl_stress_all.87483962870280113601763070138850038788546180340536587290346202949302587384298
Line 16772, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 35551549085 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 35551549085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

10.lc_ctrl_stress_all.104072317380344688688223700360456543136291786621414784112666001404775322026353
Line 5482, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 2166492789 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 2166492789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
- 11.lc_ctrl_stress_all_with_rand_reset.81880762598878614658056505918440614306321717961147252111871799843358853248049
  Line 892, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 183378769 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 183378769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Test lc_ctrl_jtag_errors has 1 failures.

13.lc_ctrl_jtag_errors.57158475848857398503504554223388368861725021499792503535564599199524144247035
Line 795, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_jtag_errors/latest/run.log

  UVM_ERROR @ 459173447 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 459173447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:912) virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error has 2 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 2 failures.
  - 18.lc_ctrl_stress_all_with_rand_reset.64546916828652466362820157178025350234010400536814541297643310447102456960960
    Line 3644, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1716925722 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
  UVM_INFO @ 1716925722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 20.lc_ctrl_stress_all_with_rand_reset.14658852573988549862775075591072624474349449722972881253965776519426535292724
    Line 6428, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 19474503101 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
  UVM_INFO @ 19474503101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```