LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Saturday June 06 2026 03:15:30 UTC

GitHub Revision: `285e653a0b`

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	4.320s	116.239us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	0.980s	62.100us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	0.870s	16.854us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.520s	65.965us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.120s	121.277us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.140s	215.849us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	0.870s	16.854us	20	20	100.00
		lc_ctrl_csr_aliasing	1.120s	121.277us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	6.100s	556.456us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	12.240s	1.598ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.010s	41.095us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	3.680s	1.177ms	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	9.700s	440.848us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	12.860s	916.259us	49	50	98.00
V2	security_escalation	lc_ctrl_state_failure	9.700s	440.848us	50	50	100.00
		lc_ctrl_prog_failure	3.680s	1.177ms	50	50	100.00
		lc_ctrl_errors	12.860s	916.259us	49	50	98.00
		lc_ctrl_security_escalation	9.040s	1.407ms	50	50	100.00
		lc_ctrl_jtag_state_failure	33.010s	2.751ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	14.240s	920.748us	20	20	100.00
		lc_ctrl_jtag_errors	1.111m	9.114ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	11.620s	814.592us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	22.830s	5.080ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	14.240s	920.748us	20	20	100.00
		lc_ctrl_jtag_errors	1.111m	9.114ms	20	20	100.00
		lc_ctrl_jtag_access	15.250s	4.117ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	21.330s	2.614ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	2.010s	136.169us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.210s	148.468us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	11.110s	1.750ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	8.480s	2.764ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.190s	94.697us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	1.890s	183.358us	10	10	100.00
		lc_ctrl_jtag_alert_test	1.390s	1.108ms	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	31.030s	5.902ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.250s	74.609us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	2.848m	19.856ms	48	50	96.00
V2	alert_test	lc_ctrl_alert_test	1.320s	66.769us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	3.110s	147.028us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	3.110s	147.028us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	0.980s	62.100us	5	5	100.00
		lc_ctrl_csr_rw	0.870s	16.854us	20	20	100.00
		lc_ctrl_csr_aliasing	1.120s	121.277us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.210s	38.727us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	0.980s	62.100us	5	5	100.00
		lc_ctrl_csr_rw	0.870s	16.854us	20	20	100.00
		lc_ctrl_csr_aliasing	1.120s	121.277us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.210s	38.727us	20	20	100.00
V2		TOTAL			697	700	99.57
V2S	tl_intg_err	lc_ctrl_sec_cm	6.190s	519.132us	5	5	100.00
		lc_ctrl_tl_intg_err	2.250s	576.171us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	2.250s	576.171us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	12.240s	1.598ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	9.700s	440.848us	50	50	100.00
		lc_ctrl_sec_cm	6.190s	519.132us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	9.700s	440.848us	50	50	100.00
		lc_ctrl_sec_cm	6.190s	519.132us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	9.700s	440.848us	50	50	100.00
		lc_ctrl_sec_cm	6.190s	519.132us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	9.700s	440.848us	50	50	100.00
		lc_ctrl_sec_cm	6.190s	519.132us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	9.700s	440.848us	50	50	100.00
		lc_ctrl_sec_cm	6.190s	519.132us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	9.700s	440.848us	50	50	100.00
		lc_ctrl_sec_cm	6.190s	519.132us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	9.700s	440.848us	50	50	100.00
		lc_ctrl_sec_cm	6.190s	519.132us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	9.700s	440.848us	50	50	100.00
		lc_ctrl_sec_cm	6.190s	519.132us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	9.040s	1.407ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	6.100s	556.456us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	22.830s	5.080ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	12.950s	2.863ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	12.950s	2.863ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	12.280s	2.870ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	12.630s	2.901ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	12.630s	2.901ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.702m	4.583ms	27	50	54.00
V3		TOTAL			27	50	54.00
		TOTAL			1004	1030	97.48

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	25	92.59
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.85	97.24	81.91	88.25	76.84	94.36	94.27	96.09

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:1237) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 17 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 17 failures.
  - 2.lc_ctrl_stress_all_with_rand_reset.35955718924688209703563328039039269947013967221789012049634275297055728993168
    Line 157, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 399353026 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 399353026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.lc_ctrl_stress_all_with_rand_reset.7583323335718621051028900029483745664229606716826333246241565189307052743917
    Line 273, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_volatile_unlock_enabled-sim-vcs/7.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2522393730 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2522393730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 15 more failures.

UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 6 failures:

Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

5.lc_ctrl_stress_all_with_rand_reset.3335372759929594423957075088686926496225474274537642140985543280576613618271
Line 1382, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 8969344305 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 8969344305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

20.lc_ctrl_stress_all_with_rand_reset.33650970963248704285069523749494655980598016889876647348319214712433370879873
Line 3009, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_volatile_unlock_enabled-sim-vcs/20.lc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 8365201449 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 8365201449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test lc_ctrl_stress_all has 2 failures.

21.lc_ctrl_stress_all.18759986795559999770208821717101860184285962640654749688479189639024070348854
Line 5381, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_volatile_unlock_enabled-sim-vcs/21.lc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 5002567977 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 5002567977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

42.lc_ctrl_stress_all.6215149232700588811334995993814948772602888500686902653838512252376255485451
Line 2144, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_volatile_unlock_enabled-sim-vcs/42.lc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 1057669678 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1057669678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test lc_ctrl_errors has 1 failures.

38.lc_ctrl_errors.8125848066412329924695964580313912254170016334858570979076108437677342640727
Line 494, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_volatile_unlock_enabled-sim-vcs/38.lc_ctrl_errors/latest/run.log

  UVM_ERROR @ 140789837 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 140789837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:912) virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error has 3 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 3 failures.
  - 8.lc_ctrl_stress_all_with_rand_reset.81382801271510405843685398442175102288235405946537179292385332054433883116053
    Line 5799, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_volatile_unlock_enabled-sim-vcs/8.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3369771775 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
  UVM_INFO @ 3369771775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 17.lc_ctrl_stress_all_with_rand_reset.36179346841953644015375320383504683659095727686691971001110846775837121818952
    Line 10221, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_volatile_unlock_enabled-sim-vcs/17.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9389815518 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
  UVM_INFO @ 9389815518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.