285e653a0b| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | mbx_smoke | mbx_smoke | 41.300s | 5.789ms | 3 | 3 | 100.00 |
| V1 | csr_hw_reset | mbx_csr_hw_reset | 0.760s | 16.237us | 5 | 5 | 100.00 |
| V1 | csr_rw | mbx_csr_rw | 0.750s | 21.210us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | mbx_csr_bit_bash | 1.990s | 1.372ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | mbx_csr_aliasing | 0.850s | 35.467us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | mbx_csr_mem_rw_with_rand_reset | 1.100s | 118.284us | 2 | 4 | 50.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | mbx_csr_rw | 0.750s | 21.210us | 20 | 20 | 100.00 |
| mbx_csr_aliasing | 0.850s | 35.467us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 40 | 42 | 95.24 | |||
| V2 | mbx_stress | mbx_stress | 1.479m | 5.045ms | 1 | 1 | 100.00 |
| V2 | mbx_max_activity | mbx_stress_zero_delays | 1.750s | 138.092us | 0 | 1 | 0.00 |
| V2 | mbx_stress_all | mbx_stress_all | 0 | 0 | -- | ||
| V2 | mbx_imbx_oob | mbx_imbx_oob | 1.200m | 3.952ms | 4 | 4 | 100.00 |
| V2 | mbx_range_lock | 0 | 0 | -- | |||
| V2 | mbx_doe_intr_msg | mbx_doe_intr_msg | 13.240s | 1.084ms | 3 | 3 | 100.00 |
| V2 | alert_test | mbx_alert_test | 0.870s | 72.992us | 3 | 3 | 100.00 |
| V2 | intr_test | mbx_intr_test | 0.760s | 28.326us | 6 | 6 | 100.00 |
| V2 | tl_d_oob_addr_access | mbx_tl_errors | 1.370s | 170.285us | 2 | 5 | 40.00 |
| V2 | tl_d_illegal_access | mbx_tl_errors | 1.370s | 170.285us | 2 | 5 | 40.00 |
| V2 | tl_d_outstanding_access | mbx_csr_hw_reset | 0.760s | 16.237us | 5 | 5 | 100.00 |
| mbx_csr_rw | 0.750s | 21.210us | 20 | 20 | 100.00 | ||
| mbx_csr_aliasing | 0.850s | 35.467us | 5 | 5 | 100.00 | ||
| mbx_same_csr_outstanding | 0.840s | 20.492us | 3 | 3 | 100.00 | ||
| V2 | tl_d_partial_access | mbx_csr_hw_reset | 0.760s | 16.237us | 5 | 5 | 100.00 |
| mbx_csr_rw | 0.750s | 21.210us | 20 | 20 | 100.00 | ||
| mbx_csr_aliasing | 0.850s | 35.467us | 5 | 5 | 100.00 | ||
| mbx_same_csr_outstanding | 0.840s | 20.492us | 3 | 3 | 100.00 | ||
| V2 | TOTAL | 22 | 26 | 84.62 | |||
| V2S | tl_intg_err | mbx_tl_intg_err | 1.980s | 227.771us | 12 | 12 | 100.00 |
| mbx_sec_cm | 0.730s | 19.837us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | sec_cm_bus_integrity | 0 | 0 | -- | ||
| V2S | sec_cm_address_range_config_regwen_mubi | sec_cm_address_range_config_regwen_mubi | 0 | 0 | -- | ||
| V2S | TOTAL | 17 | 17 | 100.00 | |||
| V3 | stress_all_with_rand_reset | mbx_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 79 | 85 | 92.94 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 5 | 83.33 |
| V2 | 10 | 8 | 6 | 60.00 |
| V2S | 4 | 2 | 2 | 50.00 |
| V3 | 1 | 0 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 85.31 | 95.61 | 90.92 | 89.04 | 42.11 | 90.37 | 97.15 | 91.95 |
UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register has 1 failures:
0.mbx_stress_zero_delays.34154416014618293367194035902656542197939748897126101422121803066201321838967
Line 127, in log /home/runner/_work/pavona/pavona/scratch/main/mbx-sim-vcs/0.mbx_stress_zero_delays/latest/run.log
UVM_ERROR @ 138092494 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
UVM_INFO @ 138092494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface mbx_soc_reg_block, TL item: req: (cip_tl_seq_item@5737) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
1.mbx_csr_mem_rw_with_rand_reset.43698333676261553440633912599871502694491395173218762877354932256321184810670
Line 80, in log /home/runner/_work/pavona/pavona/scratch/main/mbx-sim-vcs/1.mbx_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 1064425 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface mbx_soc_reg_block, TL item: req: (cip_tl_seq_item@5737) { a_addr: 'h3f49f2f4 a_data: 'h545635a4 a_mask: 'hb a_size: 'h2 a_param: 'h0 a_source: 'he a_opcode: 'h1 a_user: 'h25399 d_param: 'h0 d_source: 'he d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 1, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 1064425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface mbx_soc_reg_block, TL item: req: (cip_tl_seq_item@3499) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
2.mbx_tl_errors.1819216738031400760042718646271123884842255068614551003556460768137994060564
Line 84, in log /home/runner/_work/pavona/pavona/scratch/main/mbx-sim-vcs/2.mbx_tl_errors/latest/run.log
UVM_ERROR @ 1517927 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface mbx_soc_reg_block, TL item: req: (cip_tl_seq_item@3499) { a_addr: 'h9084734 a_data: 'hd2cbffd1 a_mask: 'h0 a_size: 'h2 a_param: 'h0 a_source: 'h9 a_opcode: 'h1 a_user: 'h24a17 d_param: 'h0 d_source: 'h9 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 1, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 1517927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface mbx_soc_reg_block, TL item: req: (cip_tl_seq_item@3991) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
3.mbx_tl_errors.72086694309848847125086976297035053595476301417389172295718102090395811214227
Line 84, in log /home/runner/_work/pavona/pavona/scratch/main/mbx-sim-vcs/3.mbx_tl_errors/latest/run.log
UVM_ERROR @ 7170653 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface mbx_soc_reg_block, TL item: req: (cip_tl_seq_item@3991) { a_addr: 'hc31dd914 a_data: 'habdc6057 a_mask: 'h9 a_size: 'h2 a_param: 'h0 a_source: 'ha2 a_opcode: 'h1 a_user: 'h246ce d_param: 'h0 d_source: 'ha2 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 1, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 7170653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface mbx_soc_reg_block, TL item: req: (cip_tl_seq_item@6275) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
3.mbx_csr_mem_rw_with_rand_reset.28061971221133749653945655976431775027473297731941535411304612586697696267709
Line 80, in log /home/runner/_work/pavona/pavona/scratch/main/mbx-sim-vcs/3.mbx_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 1291198 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface mbx_soc_reg_block, TL item: req: (cip_tl_seq_item@6275) { a_addr: 'h2066e970 a_data: 'h303c06c4 a_mask: 'h9 a_size: 'h2 a_param: 'h0 a_source: 'ha7 a_opcode: 'h1 a_user: 'h261f4 d_param: 'h0 d_source: 'ha7 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 1, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 1291198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface mbx_soc_reg_block, TL item: req: (cip_tl_seq_item@4739) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
4.mbx_tl_errors.58859955006072779062680780135360480926852191023461196853073680782201350821020
Line 84, in log /home/runner/_work/pavona/pavona/scratch/main/mbx-sim-vcs/4.mbx_tl_errors/latest/run.log
UVM_ERROR @ 17470195 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface mbx_soc_reg_block, TL item: req: (cip_tl_seq_item@4739) { a_addr: 'he916f8f0 a_data: 'hdaa922f4 a_mask: 'hc a_size: 'h2 a_param: 'h0 a_source: 'hcf a_opcode: 'h1 a_user: 'h25f52 d_param: 'h0 d_source: 'hcf d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 1, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 17470195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---