OTP_CTRL/DRAGONFLY Simulation Results

Saturday June 06 2026 03:15:30 UTC

GitHub Revision: 285e653a0b

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	2.110s	789.352us	1	1	100.00
V1	smoke	otp_ctrl_smoke	20.680s	3.996ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	3.320s	1.846ms	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	1.920s	916.542us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	5.760s	1.014ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	8.160s	2.332ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	2.640s	141.098us	14	20	70.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	1.920s	916.542us	20	20	100.00
		otp_ctrl_csr_aliasing	8.160s	2.332ms	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.260s	160.465us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.580s	628.554us	5	5	100.00
V1		TOTAL			110	116	94.83
V2	dai_access_partition_walk	otp_ctrl_partition_walk	2.162m	6.371ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	7.050s	3.283ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	47.240s	10.060ms	10	10	100.00
		otp_ctrl_check_fail	43.110s	3.108ms	34	50	68.00
V2	regwen_during_otp_init	otp_ctrl_regwen	15.660s	6.210ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	1.119m	11.246ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	1.137m	46.843ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	49.920s	15.965ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	47.610s	35.915ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	1.372m	20.578ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.745m	57.744ms	43	50	86.00
V2	test_access	otp_ctrl_test_access	54.200s	20.992ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	12.541m	308.464ms	49	50	98.00
V2	intr_test	otp_ctrl_intr_test	2.260s	680.774us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	4.350s	754.438us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	4.420s	403.046us	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	4.420s	403.046us	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	3.320s	1.846ms	5	5	100.00
		otp_ctrl_csr_rw	1.920s	916.542us	20	20	100.00
		otp_ctrl_csr_aliasing	8.160s	2.332ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	5.440s	1.697ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	3.320s	1.846ms	5	5	100.00
		otp_ctrl_csr_rw	1.920s	916.542us	20	20	100.00
		otp_ctrl_csr_aliasing	8.160s	2.332ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	5.440s	1.697ms	20	20	100.00
V2		TOTAL			1077	1101	97.82
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	5.904m	45.041ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	5.904m	45.041ms	5	5	100.00
		otp_ctrl_tl_intg_err	39.950s	26.910ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	5.904m	45.041ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	5.904m	45.041ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	39.950s	26.910ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	20.680s	3.996ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	20.680s	3.996ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	5.904m	45.041ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	5.904m	45.041ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	5.904m	45.041ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	5.904m	45.041ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	5.904m	45.041ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	5.904m	45.041ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	5.904m	45.041ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	5.904m	45.041ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	5.904m	45.041ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	5.904m	45.041ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	5.904m	45.041ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	5.904m	45.041ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	5.904m	45.041ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	5.904m	45.041ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	5.904m	45.041ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	47.610s	35.915ms	200	200	100.00
		otp_ctrl_sec_cm	5.904m	45.041ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	47.610s	35.915ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	47.610s	35.915ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	47.610s	35.915ms	200	200	100.00
		otp_ctrl_macro_errs	1.745m	57.744ms	43	50	86.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	47.610s	35.915ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	47.610s	35.915ms	200	200	100.00
		otp_ctrl_sec_cm	5.904m	45.041ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	47.610s	35.915ms	200	200	100.00
		otp_ctrl_sec_cm	5.904m	45.041ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	47.610s	35.915ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	47.610s	35.915ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	47.610s	35.915ms	200	200	100.00
		otp_ctrl_macro_errs	1.745m	57.744ms	43	50	86.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	47.610s	35.915ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	47.610s	35.915ms	200	200	100.00
		otp_ctrl_sec_cm	5.904m	45.041ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	7.050s	3.283ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	43.110s	3.108ms	34	50	68.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	1.119m	11.246ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	1.119m	11.246ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	1.119m	11.246ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	1.119m	11.246ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	1.119m	11.246ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	20.680s	3.996ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	1.119m	11.246ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	20.680s	3.996ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	5.904m	45.041ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	15.660s	6.210ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	20.680s	3.996ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	20.680s	3.996ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.745m	57.744ms	43	50	86.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	1.826m	59.039ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	30.140s	17.236ms	0	100	0.00
V3		TOTAL			1	101	0.99
	Unmapped tests	otp_ctrl_zeroization	9.870s	3.243ms	250	250	100.00
		otp_ctrl_zeroization_with_checks	19.090s	4.596ms	250	250	100.00
		TOTAL			1713	1843	92.95

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	2	2	2	100.00
V1	9	9	8	88.89
V2	17	17	14	82.35
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
87.56	94.80	92.79	93.49	59.71	93.07	93.29	85.74

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:605) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * has 104 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 98 failures.

    • 0.otp_ctrl_stress_all_with_rand_reset.6896867351507396696646206252704042797040384882706306963681064751013757864249
      Line 102, in log /home/runner/_work/pavona/pavona/scratch/main/otp_ctrl_top_dragonfly-sim-vcs/0.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 571684838 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
        UVM_INFO @ 571684838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.otp_ctrl_stress_all_with_rand_reset.54402032467540995465598659729700463852483848971761163730848991737585998819540
      Line 102, in log /home/runner/_work/pavona/pavona/scratch/main/otp_ctrl_top_dragonfly-sim-vcs/1.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  72183655 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
        UVM_INFO @  72183655 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 96 more failures.

  • Test otp_ctrl_csr_mem_rw_with_rand_reset has 6 failures.

    • 0.otp_ctrl_csr_mem_rw_with_rand_reset.60696360067300432764370093034342581695179174343916201811567935092242425466398
      Line 96, in log /home/runner/_work/pavona/pavona/scratch/main/otp_ctrl_top_dragonfly-sim-vcs/0.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @  80592896 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
        UVM_INFO @  80592896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.otp_ctrl_csr_mem_rw_with_rand_reset.28754083220634974051682045328404564426488006512333125756411383653247615708819
      Line 96, in log /home/runner/_work/pavona/pavona/scratch/main/otp_ctrl_top_dragonfly-sim-vcs/2.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @ 137294745 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
        UVM_INFO @ 137294745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 4 more failures.

• UVM_ERROR (otp_ctrl_scoreboard.sv:1658) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 24 failures:

  • Test otp_ctrl_macro_errs has 7 failures.

    • 0.otp_ctrl_macro_errs.10440875484519300434663307922366140652069248200238507359826578238252145041330
      Line 106, in log /home/runner/_work/pavona/pavona/scratch/main/otp_ctrl_top_dragonfly-sim-vcs/0.otp_ctrl_macro_errs/latest/run.log

        UVM_ERROR @ 10948372456 ps: (otp_ctrl_scoreboard.sv:1658) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2049 [0x801]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 10948372456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 10.otp_ctrl_macro_errs.46928595178868609818340747567830386001303950116368087448310379781122885826388
      Line 102, in log /home/runner/_work/pavona/pavona/scratch/main/otp_ctrl_top_dragonfly-sim-vcs/10.otp_ctrl_macro_errs/latest/run.log

        UVM_ERROR @ 596038750 ps: (otp_ctrl_scoreboard.sv:1658) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1025 [0x401]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 596038750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 5 more failures.

  • Test otp_ctrl_check_fail has 16 failures.

    • 1.otp_ctrl_check_fail.7241147183810192578912767999054415738997507093501572611722250327452233406833
      Line 101, in log /home/runner/_work/pavona/pavona/scratch/main/otp_ctrl_top_dragonfly-sim-vcs/1.otp_ctrl_check_fail/latest/run.log

        UVM_ERROR @ 715315882 ps: (otp_ctrl_scoreboard.sv:1658) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 512 [0x200]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 715315882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.otp_ctrl_check_fail.89689272465164235958990912722429838807739775756647006448506809130663049582363
      Line 100, in log /home/runner/_work/pavona/pavona/scratch/main/otp_ctrl_top_dragonfly-sim-vcs/2.otp_ctrl_check_fail/latest/run.log

        UVM_ERROR @ 4857817409 ps: (otp_ctrl_scoreboard.sv:1658) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 4 [0x4]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 4857817409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 14 more failures.

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 24.otp_ctrl_stress_all_with_rand_reset.18307560652393186611865416382513600530321888628649038464395285603050591680302
      Line 125, in log /home/runner/_work/pavona/pavona/scratch/main/otp_ctrl_top_dragonfly-sim-vcs/24.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 20778603393 ps: (otp_ctrl_scoreboard.sv:1658) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3261181472 [0xc261ae20] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 20778603393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_scoreboard.sv:1116) [scoreboard] Check failed (csr.get_mirrored_value() | status_mask) == (item.d_data | status_mask) (* [*] vs * [*]) reg name: status, compare_mask * has 1 failures:

  • Test otp_ctrl_stress_all has 1 failures.

    • 19.otp_ctrl_stress_all.69932685719337144236736045304999440855753799772510712013204655026674243361146
      Line 132, in log /home/runner/_work/pavona/pavona/scratch/main/otp_ctrl_top_dragonfly-sim-vcs/19.otp_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 97591925092 ps: (otp_ctrl_scoreboard.sv:1116) [uvm_test_top.env.scoreboard] Check failed (csr.get_mirrored_value() | status_mask) == (item.d_data | status_mask) (257 [0x101] vs 259 [0x103]) reg name: status, compare_mask 0
        UVM_INFO @ 97591925092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_scoreboard.sv:1658) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 26.otp_ctrl_stress_all_with_rand_reset.104362432175841322877093012407498355179184058195279049128703538187387913162045
      Line 98, in log /home/runner/_work/pavona/pavona/scratch/main/otp_ctrl_top_dragonfly-sim-vcs/26.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4169724415 ps: (otp_ctrl_scoreboard.sv:1658) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 5 [0x5]) reg name: otp_ctrl_core_reg_block.err_code_26
        UVM_INFO @ 4169724415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---