OTP_CTRL/EGRET Simulation Results

Saturday June 06 2026 03:15:30 UTC

GitHub Revision: `285e653a0b`

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.050s	91.480us	1	1	100.00
V1	smoke	otp_ctrl_smoke	53.160s	11.999ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	1.660s	231.537us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	1.790s	91.467us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	5.430s	1.528ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	5.730s	654.108us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	2.610s	231.209us	16	20	80.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	1.790s	91.467us	20	20	100.00
		otp_ctrl_csr_aliasing	5.730s	654.108us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.800s	498.854us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.350s	578.144us	5	5	100.00
V1		TOTAL			112	116	96.55
V2	dai_access_partition_walk	otp_ctrl_partition_walk	10.580s	2.371ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	6.570s	2.373ms	296	300	98.67
V2	partition_check	otp_ctrl_background_chks	26.270s	1.816ms	10	10	100.00
		otp_ctrl_check_fail	31.410s	25.295ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	12.530s	5.771ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	23.330s	2.240ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	31.330s	3.016ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	30.410s	13.722ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	22.360s	12.361ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	38.400s	14.214ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.253m	35.516ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	29.260s	6.038ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	3.346m	32.480ms	49	50	98.00
V2	intr_test	otp_ctrl_intr_test	1.600s	575.953us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	2.770s	1.158ms	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	5.040s	2.631ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	5.040s	2.631ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	1.660s	231.537us	5	5	100.00
		otp_ctrl_csr_rw	1.790s	91.467us	20	20	100.00
		otp_ctrl_csr_aliasing	5.730s	654.108us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.090s	1.681ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	1.660s	231.537us	5	5	100.00
		otp_ctrl_csr_rw	1.790s	91.467us	20	20	100.00
		otp_ctrl_csr_aliasing	5.730s	654.108us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.090s	1.681ms	20	20	100.00
V2		TOTAL			1096	1101	99.55
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	2.061m	42.129ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	2.061m	42.129ms	5	5	100.00
		otp_ctrl_tl_intg_err	16.440s	20.060ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	2.061m	42.129ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	2.061m	42.129ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	16.440s	20.060ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	53.160s	11.999ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	53.160s	11.999ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	2.061m	42.129ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	2.061m	42.129ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	2.061m	42.129ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	2.061m	42.129ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	2.061m	42.129ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	2.061m	42.129ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	2.061m	42.129ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	2.061m	42.129ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	2.061m	42.129ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	2.061m	42.129ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	2.061m	42.129ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	2.061m	42.129ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	2.061m	42.129ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	2.061m	42.129ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	2.061m	42.129ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	22.360s	12.361ms	200	200	100.00
		otp_ctrl_sec_cm	2.061m	42.129ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	22.360s	12.361ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	22.360s	12.361ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	22.360s	12.361ms	200	200	100.00
		otp_ctrl_macro_errs	1.253m	35.516ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	22.360s	12.361ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	22.360s	12.361ms	200	200	100.00
		otp_ctrl_sec_cm	2.061m	42.129ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	22.360s	12.361ms	200	200	100.00
		otp_ctrl_sec_cm	2.061m	42.129ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	22.360s	12.361ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	22.360s	12.361ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	22.360s	12.361ms	200	200	100.00
		otp_ctrl_macro_errs	1.253m	35.516ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	22.360s	12.361ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	22.360s	12.361ms	200	200	100.00
		otp_ctrl_sec_cm	2.061m	42.129ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	6.570s	2.373ms	296	300	98.67
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	31.410s	25.295ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	23.330s	2.240ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	23.330s	2.240ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	23.330s	2.240ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	23.330s	2.240ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	23.330s	2.240ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	53.160s	11.999ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	23.330s	2.240ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	53.160s	11.999ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	2.061m	42.129ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	12.530s	5.771ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	53.160s	11.999ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	53.160s	11.999ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.253m	35.516ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	10.610s	3.007ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	24.730s	16.650ms	0	100	0.00
V3		TOTAL			1	101	0.99
	Unmapped tests	otp_ctrl_zeroization	7.470s	1.581ms	250	250	100.00
		otp_ctrl_zeroization_with_checks	10.650s	1.967ms	250	250	100.00
		TOTAL			1734	1843	94.09

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	2	2	2	100.00
V1	9	9	8	88.89
V2	17	17	15	88.24
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
87.87	90.35	91.85	95.63	64.24	85.95	94.69	92.40

Failure Buckets

UVM_ERROR (cip_base_scoreboard.sv:605) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * has 104 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 100 failures.
  - 0.otp_ctrl_stress_all_with_rand_reset.43044658490201300834008043644420470530549018121649626827925934419193594907985
    Line 116, in log /home/runner/_work/pavona/pavona/scratch/main/otp_ctrl_top_egret-sim-vcs/0.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 758782805 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
  UVM_INFO @ 758782805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.otp_ctrl_stress_all_with_rand_reset.69140057326362220064998951789841097945937281454407069607137401023448421760087
    Line 102, in log /home/runner/_work/pavona/pavona/scratch/main/otp_ctrl_top_egret-sim-vcs/1.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 429482537 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
  UVM_INFO @ 429482537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 98 more failures.
- Test otp_ctrl_csr_mem_rw_with_rand_reset has 4 failures.
  - 10.otp_ctrl_csr_mem_rw_with_rand_reset.78985160975203084293465818014273865357997059593371177763273041133620406687938
    Line 101, in log /home/runner/_work/pavona/pavona/scratch/main/otp_ctrl_top_egret-sim-vcs/10.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 107425817 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
  UVM_INFO @ 107425817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 13.otp_ctrl_csr_mem_rw_with_rand_reset.32638699703260229931469673829865074520231998864751795568068939329407942424146
    Line 101, in log /home/runner/_work/pavona/pavona/scratch/main/otp_ctrl_top_egret-sim-vcs/13.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 426325075 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
  UVM_INFO @ 426325075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

UVM_ERROR (cip_base_vseq.sv:1316) [otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_check_error does not trigger!

has 4 failures:

Test otp_ctrl_init_fail has 4 failures.

142.otp_ctrl_init_fail.111913313717120197601159575073313660728725465329760178828024358420533930120281
Line 97, in log /home/runner/_work/pavona/pavona/scratch/main/otp_ctrl_top_egret-sim-vcs/142.otp_ctrl_init_fail/latest/run.log

  UVM_ERROR @ 104185650 ps: (cip_base_vseq.sv:1316) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
  UVM_INFO @ 104185650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

167.otp_ctrl_init_fail.62438121883465045055793965640987724978926341624578271520992120711314792975247
Line 97, in log /home/runner/_work/pavona/pavona/scratch/main/otp_ctrl_top_egret-sim-vcs/167.otp_ctrl_init_fail/latest/run.log

  UVM_ERROR @ 364144863 ps: (cip_base_vseq.sv:1316) [uvm_test_top.env.virtual_sequencer.otp_ctrl_init_fail_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
  UVM_INFO @ 364144863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert fatal_check_error did not trigger max_delay:* has 1 failures:
- Test otp_ctrl_stress_all has 1 failures.
  - 1.otp_ctrl_stress_all.24768414030186242613367787830947946423179794783673973317728379646335021249746
    Line 126, in log /home/runner/_work/pavona/pavona/scratch/main/otp_ctrl_top_egret-sim-vcs/1.otp_ctrl_stress_all/latest/run.log
```
  UVM_ERROR @ 1866528524 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_check_error did not trigger max_delay:5
  UVM_INFO @ 1866528524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```