PATTGEN Simulation Results

Saturday June 06 2026 03:15:30 UTC

GitHub Revision: `285e653a0b`

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	1.890s	96.932us	5	5	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	0.450s	15.976us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	0.490s	13.435us	10	10	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	1.430s	784.757us	3	3	100.00
V1	csr_aliasing	pattgen_csr_aliasing	0.570s	75.942us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	0.730s	28.367us	5	5	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	0.490s	13.435us	10	10	100.00
		pattgen_csr_aliasing	0.570s	75.942us	5	5	100.00
V1		TOTAL			33	33	100.00
V2	perf	pattgen_perf	18.705m	600.000ms	2	4	50.00
V2	cnt_rollover	cnt_rollover	40.210s	8.049ms	5	5	100.00
V2	error	pattgen_error	0.500s	34.080us	1	1	100.00
V2	stress_all	pattgen_stress_all	1.836h	5.463s	7	8	87.50
V2	alert_test	pattgen_alert_test	0.450s	29.352us	3	3	100.00
V2	intr_test	pattgen_intr_test	0.490s	122.868us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	1.260s	1.235ms	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	1.260s	1.235ms	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	0.450s	15.976us	5	5	100.00
		pattgen_csr_rw	0.490s	13.435us	10	10	100.00
		pattgen_csr_aliasing	0.570s	75.942us	5	5	100.00
		pattgen_same_csr_outstanding	0.700s	29.510us	33	33	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	0.450s	15.976us	5	5	100.00
		pattgen_csr_rw	0.490s	13.435us	10	10	100.00
		pattgen_csr_aliasing	0.570s	75.942us	5	5	100.00
		pattgen_same_csr_outstanding	0.700s	29.510us	33	33	100.00
V2		TOTAL			121	124	97.58
V2S	tl_intg_err	pattgen_tl_intg_err	0.920s	295.287us	45	45	100.00
		pattgen_sec_cm	0.560s	325.625us	3	3	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	0.920s	295.287us	45	45	100.00
V2S		TOTAL			48	48	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	59.980s	14.493ms	1	4	25.00
V3		TOTAL			1	4	25.00
	Unmapped tests	pattgen_inactive_level	2.290s	374.811us	5	5	100.00
		TOTAL			208	214	97.20

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	6	6	6	100.00
V2	8	8	6	75.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.01	99.82	99.52	100.00	--	100.00	96.95	67.74

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:1237) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:

Test pattgen_stress_all_with_rand_reset has 3 failures.

1.pattgen_stress_all_with_rand_reset.13796228697094793645149253902127996543241390202535308402786748721197006102458
Line 218, in log /home/runner/_work/pavona/pavona/scratch/main/pattgen-sim-vcs/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2490048482 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 2490056892 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 2490056892 ps: (cip_base_vseq.sv:1154) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 1/10
  UVM_INFO @ 2490376892 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

2.pattgen_stress_all_with_rand_reset.36175737223110174844177814701517859383913866406459582756977174130291601111959
Line 274, in log /home/runner/_work/pavona/pavona/scratch/main/pattgen-sim-vcs/2.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2843077307 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 2843079401 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 2843079401 ps: (cip_base_vseq.sv:1154) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 2/5
  UVM_INFO @ 2843329403 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 1 more failures.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test pattgen_perf has 1 failures.
  - 2.pattgen_perf.2027531251163972549010691230304458457641818669876030649967920805640786798837
    Line 106, in log /home/runner/_work/pavona/pavona/scratch/main/pattgen-sim-vcs/2.pattgen_perf/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job timed out after * minutes has 1 failures:
- Test pattgen_perf has 1 failures.
  - 3.pattgen_perf.62877415578250367709760657801455136690473745709824657548130563951372709091820
    Log /home/runner/_work/pavona/pavona/scratch/main/pattgen-sim-vcs/3.pattgen_perf/latest/run.log
```
  Job timed out after 60 minutes
```
UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: has 1 failures:
- Test pattgen_stress_all has 1 failures.
  - 6.pattgen_stress_all.96642453844614190508670057441389342036145556143310187427277495407742554612621
    Line 194, in log /home/runner/_work/pavona/pavona/scratch/main/pattgen-sim-vcs/6.pattgen_stress_all/latest/run.log
```
  UVM_ERROR @ 9570473683 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
  -----------------------------------
  Name      Type          Size  Value
  -----------------------------------
  exp_item  pattgen_item  -     @8862
```