PRIM_ALERT Simulation Results

Saturday June 06 2026 03:15:30 UTC

GitHub Revision: 285e653a0b

Branch: main

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 prim_alert_request_test prim_async_alert 0.360s 11.503us 19 20 95.00
prim_async_fatal_alert 0.360s 31.639us 19 20 95.00
prim_sync_alert 0.370s 9.571us 20 20 100.00
prim_sync_fatal_alert 0.430s 27.089us 20 20 100.00
V1 prim_alert_test prim_async_alert 0.360s 11.503us 19 20 95.00
prim_async_fatal_alert 0.360s 31.639us 19 20 95.00
prim_sync_alert 0.370s 9.571us 20 20 100.00
prim_sync_fatal_alert 0.430s 27.089us 20 20 100.00
V1 prim_alert_ping_request_test prim_async_alert 0.360s 11.503us 19 20 95.00
prim_async_fatal_alert 0.360s 31.639us 19 20 95.00
prim_sync_alert 0.370s 9.571us 20 20 100.00
prim_sync_fatal_alert 0.430s 27.089us 20 20 100.00
V1 prim_alert_integrity_errors_test prim_async_alert 0.360s 11.503us 19 20 95.00
prim_async_fatal_alert 0.360s 31.639us 19 20 95.00
prim_sync_alert 0.370s 9.571us 20 20 100.00
prim_sync_fatal_alert 0.430s 27.089us 20 20 100.00
V1 TOTAL 78 80 97.50
V2 prim_alert_init_trigger_test prim_async_alert 0.360s 11.503us 19 20 95.00
prim_async_fatal_alert 0.360s 31.639us 19 20 95.00
prim_sync_alert 0.370s 9.571us 20 20 100.00
prim_sync_fatal_alert 0.430s 27.089us 20 20 100.00
V2 TOTAL 0 0 --
V2S TOTAL 0 0 --
V3 prim_alert_gate_sender_clk_rst_test prim_alert_gate_sender_clk_rst_test 0 0 --
V3 TOTAL 0 0 --
Unmapped tests prim_async_fatal_alert_with_3_cycles_skew 0.370s 30.462us 20 20 100.00
TOTAL 98 100 98.00

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 1 100.00
V1 4 4 2 50.00
V3 1 0 0 0.00

Coverage Results

SCORE LINE COND TOGGLE FSM BRANCH ASSERT
95.19 100.00 100.00 100.00 89.29 95.83 86.05

Failure Buckets