PWM/EGRET Simulation Results

Saturday June 06 2026 03:15:30 UTC

GitHub Revision: 285e653a0b

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwm_smoke	2.480s	534.148us	10	10	100.00
V1	csr_hw_reset	pwm_csr_hw_reset	0.720s	104.995us	5	5	100.00
V1	csr_rw	pwm_csr_rw	0.680s	17.724us	20	20	100.00
V1	csr_bit_bash	pwm_csr_bit_bash	3.600s	3.511ms	5	5	100.00
V1	csr_aliasing	pwm_csr_aliasing	1.300s	83.716us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwm_csr_mem_rw_with_rand_reset	0.850s	60.662us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwm_csr_rw	0.680s	17.724us	20	20	100.00
		pwm_csr_aliasing	1.300s	83.716us	5	5	100.00
V1		TOTAL			65	65	100.00
V2	dutycycle	pwm_rand_output	37.490s	20.998ms	25	25	100.00
V2	pulse	pwm_rand_output	37.490s	20.998ms	25	25	100.00
V2	blink	pwm_rand_output	37.490s	20.998ms	25	25	100.00
V2	heartbeat	pwm_rand_output	37.490s	20.998ms	25	25	100.00
V2	resolution	pwm_rand_output	37.490s	20.998ms	25	25	100.00
V2	multi_channel	pwm_rand_output	37.490s	20.998ms	25	25	100.00
V2	polarity	pwm_rand_output	37.490s	20.998ms	25	25	100.00
V2	phase	pwm_rand_output	37.490s	20.998ms	25	25	100.00
		pwm_phase	26.980s	52.491ms	25	25	100.00
V2	lowpower	pwm_rand_output	37.490s	20.998ms	25	25	100.00
V2	perf	pwm_perf	33.000s	10.503ms	10	10	100.00
V2	regwen	pwm_regwen	1.471m	42.011ms	1	1	100.00
V2	stress_all	pwm_stress_all	1.599m	81.123ms	25	25	100.00
V2	alert_test	pwm_alert_test	0.730s	25.544us	50	50	100.00
V2	intr_test	pwm_intr_test			0	0	--
V2	tl_d_oob_addr_access	pwm_tl_errors	1.780s	129.349us	20	20	100.00
V2	tl_d_illegal_access	pwm_tl_errors	1.780s	129.349us	20	20	100.00
V2	tl_d_outstanding_access	pwm_csr_hw_reset	0.720s	104.995us	5	5	100.00
		pwm_csr_rw	0.680s	17.724us	20	20	100.00
		pwm_csr_aliasing	1.300s	83.716us	5	5	100.00
		pwm_same_csr_outstanding	0.890s	59.643us	20	20	100.00
V2	tl_d_partial_access	pwm_csr_hw_reset	0.720s	104.995us	5	5	100.00
		pwm_csr_rw	0.680s	17.724us	20	20	100.00
		pwm_csr_aliasing	1.300s	83.716us	5	5	100.00
		pwm_same_csr_outstanding	0.890s	59.643us	20	20	100.00
V2		TOTAL			176	176	100.00
V2S	tl_intg_err	pwm_tl_intg_err	1.440s	135.710us	20	20	100.00
		pwm_sec_cm	1.150s	154.099us	5	5	100.00
V2S	sec_cm_bus_integrity	pwm_tl_intg_err	1.440s	135.710us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	heartbeat_wrap	pwm_heartbeat_wrap	28.580s	21.007ms	10	10	100.00
V3		TOTAL			10	10	100.00
		TOTAL			276	276	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	8	8	88.89
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.50	99.61	93.91	91.96	--	98.85	98.00	78.68