PWRMGR/DRAGONFLY Simulation Results

Saturday June 06 2026 03:15:30 UTC

GitHub Revision: 285e653a0b

Branch: main

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwrmgr_smoke 0.760s 26.329us 50 50 100.00
V1 csr_hw_reset pwrmgr_csr_hw_reset 0.530s 49.076us 5 5 100.00
V1 csr_rw pwrmgr_csr_rw 0.530s 64.105us 20 20 100.00
V1 csr_bit_bash pwrmgr_csr_bit_bash 2.000s 1.030ms 5 5 100.00
V1 csr_aliasing pwrmgr_csr_aliasing 0.650s 47.495us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwrmgr_csr_mem_rw_with_rand_reset 0.930s 125.368us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwrmgr_csr_rw 0.530s 64.105us 20 20 100.00
pwrmgr_csr_aliasing 0.650s 47.495us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 wakeup pwrmgr_wakeup 0.970s 312.385us 50 50 100.00
V2 control_clks pwrmgr_wakeup 0.970s 312.385us 50 50 100.00
V2 aborted_low_power pwrmgr_aborted_low_power 1.130s 45.144us 50 50 100.00
pwrmgr_lowpower_invalid 0.790s 80.568us 50 50 100.00
V2 reset pwrmgr_reset 0.990s 106.384us 47 50 94.00
pwrmgr_reset_invalid 1.030s 111.100us 47 50 94.00
V2 main_power_glitch_reset pwrmgr_reset 0.990s 106.384us 47 50 94.00
V2 reset_wakeup_race pwrmgr_wakeup_reset 1.220s 297.781us 50 50 100.00
V2 lowpower_wakeup_race pwrmgr_lowpower_wakeup_race 1.130s 303.337us 50 50 100.00
V2 disable_rom_integrity_check pwrmgr_disable_rom_integrity_check 0.800s 67.819us 5 50 10.00
V2 stress_all pwrmgr_stress_all 3.930s 2.244ms 50 50 100.00
V2 intr_test pwrmgr_intr_test 0.580s 20.440us 50 50 100.00
V2 tl_d_oob_addr_access pwrmgr_tl_errors 1.640s 146.411us 20 20 100.00
V2 tl_d_illegal_access pwrmgr_tl_errors 1.640s 146.411us 20 20 100.00
V2 tl_d_outstanding_access pwrmgr_csr_hw_reset 0.530s 49.076us 5 5 100.00
pwrmgr_csr_rw 0.530s 64.105us 20 20 100.00
pwrmgr_csr_aliasing 0.650s 47.495us 5 5 100.00
pwrmgr_same_csr_outstanding 0.670s 44.938us 20 20 100.00
V2 tl_d_partial_access pwrmgr_csr_hw_reset 0.530s 49.076us 5 5 100.00
pwrmgr_csr_rw 0.530s 64.105us 20 20 100.00
pwrmgr_csr_aliasing 0.650s 47.495us 5 5 100.00
pwrmgr_same_csr_outstanding 0.670s 44.938us 20 20 100.00
V2 TOTAL 489 540 90.56
V2S tl_intg_err pwrmgr_tl_intg_err 1.110s 182.215us 20 20 100.00
pwrmgr_sec_cm 1.980s 615.227us 5 5 100.00
V2S prim_count_check pwrmgr_sec_cm 1.980s 615.227us 5 5 100.00
V2S prim_fsm_check pwrmgr_sec_cm 1.980s 615.227us 5 5 100.00
V2S sec_cm_bus_integrity pwrmgr_tl_intg_err 1.110s 182.215us 20 20 100.00
V2S sec_cm_lc_ctrl_intersig_mubi pwrmgr_sec_cm_lc_ctrl_intersig_mubi 2.330s 755.965us 50 50 100.00
V2S sec_cm_rom_ctrl_intersig_mubi pwrmgr_wakeup_reset 1.220s 297.781us 50 50 100.00
pwrmgr_repeat_wakeup_reset 0 0 --
V2S sec_cm_rstmgr_intersig_mubi pwrmgr_sec_cm_rstmgr_intersig_mubi 0.980s 71.632us 50 50 100.00
V2S sec_cm_esc_rx_clk_bkgn_chk pwrmgr_esc_clk_rst_malfunc 0.660s 48.683us 25 50 50.00
V2S sec_cm_esc_rx_clk_local_esc pwrmgr_sec_cm 1.980s 615.227us 5 5 100.00
V2S sec_cm_fsm_sparse pwrmgr_sec_cm 1.980s 615.227us 5 5 100.00
V2S sec_cm_fsm_terminal pwrmgr_sec_cm 1.980s 615.227us 5 5 100.00
V2S sec_cm_ctrl_flow_global_esc pwrmgr_global_esc 0.680s 24.682us 50 50 100.00
V2S sec_cm_main_pd_rst_local_esc pwrmgr_glitch 0.720s 98.694us 50 50 100.00
V2S sec_cm_ctrl_config_regwen pwrmgr_sec_cm_ctrl_config_regwen 1.160s 287.352us 50 50 100.00
V2S sec_cm_wakeup_config_regwen pwrmgr_csr_rw 0.530s 64.105us 20 20 100.00
V2S sec_cm_reset_config_regwen pwrmgr_csr_rw 0.530s 64.105us 20 20 100.00
V2S TOTAL 300 325 92.31
V3 escalation_timeout pwrmgr_escalation_timeout 0.750s 172.736us 0 50 0.00
V3 stress_all_with_rand_reset pwrmgr_stress_all_with_rand_reset 11.900s 9.017ms 42 50 84.00
V3 TOTAL 42 100 42.00
TOTAL 936 1070 87.48

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 12 12 9 75.00
V2S 9 8 7 77.78
V3 2 2 0 0.00

Coverage Results

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
93.44 99.24 96.72 96.87 96.00 97.19 97.22 70.84

Failure Buckets