PWRMGR/EGRET Simulation Results

Saturday June 06 2026 03:15:30 UTC

GitHub Revision: 285e653a0b

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.780s	22.771us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.510s	29.543us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.640s	140.678us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	1.860s	322.313us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	0.690s	76.970us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	0.800s	60.097us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.640s	140.678us	20	20	100.00
		pwrmgr_csr_aliasing	0.690s	76.970us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.210s	282.292us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.210s	282.292us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	1.070s	40.379us	50	50	100.00
		pwrmgr_lowpower_invalid	0.850s	46.722us	50	50	100.00
V2	reset	pwrmgr_reset	2.360s	1.000ms	40	50	80.00
		pwrmgr_reset_invalid	1.040s	109.839us	41	50	82.00
V2	main_power_glitch_reset	pwrmgr_reset	2.360s	1.000ms	40	50	80.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.390s	313.523us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.090s	269.645us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	2.140s	1.000ms	36	50	72.00
V2	stress_all	pwrmgr_stress_all	16.580s	10.822ms	35	50	70.00
V2	intr_test	pwrmgr_intr_test	0.610s	20.077us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	1.440s	605.196us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	1.440s	605.196us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.510s	29.543us	5	5	100.00
		pwrmgr_csr_rw	0.640s	140.678us	20	20	100.00
		pwrmgr_csr_aliasing	0.690s	76.970us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.680s	32.093us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.510s	29.543us	5	5	100.00
		pwrmgr_csr_rw	0.640s	140.678us	20	20	100.00
		pwrmgr_csr_aliasing	0.690s	76.970us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.680s	32.093us	20	20	100.00
V2		TOTAL			492	540	91.11
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.040s	181.499us	20	20	100.00
		pwrmgr_sec_cm	1.470s	931.794us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	1.470s	931.794us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	1.470s	931.794us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.040s	181.499us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	2.490s	778.881us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_wakeup_reset	1.390s	313.523us	50	50	100.00
		pwrmgr_repeat_wakeup_reset			0	0	--
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	0.930s	47.066us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.710s	8.242us	30	50	60.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	1.470s	931.794us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	1.470s	931.794us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	1.470s	931.794us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.820s	40.635us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.730s	95.148us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.380s	270.093us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.640s	140.678us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.640s	140.678us	20	20	100.00
V2S		TOTAL			305	325	93.85
V3	escalation_timeout	pwrmgr_escalation_timeout	0.860s	91.727us	0	50	0.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	11.860s	13.602ms	43	50	86.00
V3		TOTAL			43	100	43.00
		TOTAL			945	1070	88.32

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	8	66.67
V2S	9	8	7	77.78
V3	2	2	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.70	99.09	96.79	99.62	96.00	96.21	97.19	99.01

Failure Buckets

• UVM_ERROR (pwrmgr_sec_cm_checker_assert.sv:166) [ASSERT FAILED] EscClkStopEscTimeout_A has 70 failures:

  • Test pwrmgr_escalation_timeout has 50 failures.

    • 0.pwrmgr_escalation_timeout.97083206884392001690535834346324538176103099811761355296713458713885156630788
      Line 82, in log /home/runner/_work/pavona/pavona/scratch/main/pwrmgr_top_egret-sim-vcs/0.pwrmgr_escalation_timeout/latest/run.log

        UVM_ERROR @ 101948853 ps: (pwrmgr_sec_cm_checker_assert.sv:166) [ASSERT FAILED] EscClkStopEscTimeout_A
        UVM_INFO @ 101948853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.pwrmgr_escalation_timeout.111442121261349849406195111565955026723190758400687588256579162300768474974984
      Line 77, in log /home/runner/_work/pavona/pavona/scratch/main/pwrmgr_top_egret-sim-vcs/1.pwrmgr_escalation_timeout/latest/run.log

        UVM_ERROR @ 340094433 ps: (pwrmgr_sec_cm_checker_assert.sv:166) [ASSERT FAILED] EscClkStopEscTimeout_A
        UVM_INFO @ 340094433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 48 more failures.

  • Test pwrmgr_esc_clk_rst_malfunc has 20 failures.

    • 1.pwrmgr_esc_clk_rst_malfunc.6019948958123606227910085125022136968928165454139754357389289378582297056605
      Line 77, in log /home/runner/_work/pavona/pavona/scratch/main/pwrmgr_top_egret-sim-vcs/1.pwrmgr_esc_clk_rst_malfunc/latest/run.log

        UVM_ERROR @   7815864 ps: (pwrmgr_sec_cm_checker_assert.sv:166) [ASSERT FAILED] EscClkStopEscTimeout_A
        UVM_INFO @   7815864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.pwrmgr_esc_clk_rst_malfunc.28759033330439040357531008523707540281403203617941094501047276458804784415740
      Line 77, in log /home/runner/_work/pavona/pavona/scratch/main/pwrmgr_top_egret-sim-vcs/3.pwrmgr_esc_clk_rst_malfunc/latest/run.log

        UVM_ERROR @   7372579 ps: (pwrmgr_sec_cm_checker_assert.sv:166) [ASSERT FAILED] EscClkStopEscTimeout_A
        UVM_INFO @   7372579 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 18 more failures.

• Offending 'rstreqs[pwrmgr_reg_pkg::ResetEscIdx]' has 15 failures:

  • Test pwrmgr_reset has 3 failures.

    • 0.pwrmgr_reset.19207082212708623574302265490185948875166226048521816102365878217752519048584
      Line 101, in log /home/runner/_work/pavona/pavona/scratch/main/pwrmgr_top_egret-sim-vcs/0.pwrmgr_reset/latest/run.log

            Offending 'rstreqs[pwrmgr_reg_pkg::ResetEscIdx]'
        UVM_ERROR @  15161585 ps: (pwrmgr_rstreqs_sva_if.sv:88) [ASSERT FAILED] EscRstOn_A
        UVM_INFO @  15161585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • 12.pwrmgr_reset.47609586916521993268725699930186279230131964989199820179038561883678327052475
      Line 90, in log /home/runner/_work/pavona/pavona/scratch/main/pwrmgr_top_egret-sim-vcs/12.pwrmgr_reset/latest/run.log

            Offending 'rstreqs[pwrmgr_reg_pkg::ResetEscIdx]'
        UVM_ERROR @  12581058 ps: (pwrmgr_rstreqs_sva_if.sv:88) [ASSERT FAILED] EscRstOn_A
        UVM_INFO @  12581058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • ... and 1 more failures.

  • Test pwrmgr_disable_rom_integrity_check has 6 failures.

    • 5.pwrmgr_disable_rom_integrity_check.43252600395663701307372344677034961861960556243726381478699953879804643608625
      Line 199, in log /home/runner/_work/pavona/pavona/scratch/main/pwrmgr_top_egret-sim-vcs/5.pwrmgr_disable_rom_integrity_check/latest/run.log

            Offending 'rstreqs[pwrmgr_reg_pkg::ResetEscIdx]'
        UVM_ERROR @ 146744267 ps: (pwrmgr_rstreqs_sva_if.sv:88) [ASSERT FAILED] EscRstOn_A
        UVM_INFO @ 146744267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • 15.pwrmgr_disable_rom_integrity_check.49352406424754257719256460753165829093640823284883229094932519621678508705917
      Line 105, in log /home/runner/_work/pavona/pavona/scratch/main/pwrmgr_top_egret-sim-vcs/15.pwrmgr_disable_rom_integrity_check/latest/run.log

            Offending 'rstreqs[pwrmgr_reg_pkg::ResetEscIdx]'
        UVM_ERROR @  12005656 ps: (pwrmgr_rstreqs_sva_if.sv:88) [ASSERT FAILED] EscRstOn_A
        UVM_INFO @  12005656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • ... and 4 more failures.

  • Test pwrmgr_stress_all has 2 failures.

    • 11.pwrmgr_stress_all.64578941601234136816625096132145463777072841990316054367269566180332697889574
      Line 970, in log /home/runner/_work/pavona/pavona/scratch/main/pwrmgr_top_egret-sim-vcs/11.pwrmgr_stress_all/latest/run.log

            Offending 'rstreqs[pwrmgr_reg_pkg::ResetEscIdx]'
        UVM_ERROR @ 938457736 ps: (pwrmgr_rstreqs_sva_if.sv:88) [ASSERT FAILED] EscRstOn_A
        UVM_INFO @ 938457736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • 17.pwrmgr_stress_all.64765485119949512047702711678325679681946171760833395109363664661495752888042
      Line 905, in log /home/runner/_work/pavona/pavona/scratch/main/pwrmgr_top_egret-sim-vcs/17.pwrmgr_stress_all/latest/run.log

            Offending 'rstreqs[pwrmgr_reg_pkg::ResetEscIdx]'
        UVM_ERROR @ 1351892819 ps: (pwrmgr_rstreqs_sva_if.sv:88) [ASSERT FAILED] EscRstOn_A
        UVM_INFO @ 1351892819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test pwrmgr_stress_all_with_rand_reset has 4 failures.

    • 31.pwrmgr_stress_all_with_rand_reset.41853229014752599754789445745150671536232518595643756696743543517628748861244
      Line 751, in log /home/runner/_work/pavona/pavona/scratch/main/pwrmgr_top_egret-sim-vcs/31.pwrmgr_stress_all_with_rand_reset/latest/run.log

            Offending 'rstreqs[pwrmgr_reg_pkg::ResetEscIdx]'
        UVM_ERROR @ 786219435 ps: (pwrmgr_rstreqs_sva_if.sv:88) [ASSERT FAILED] EscRstOn_A
        UVM_INFO @ 786219435 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • 33.pwrmgr_stress_all_with_rand_reset.52253437674408134621265100997974367569796861647549018299984510811057312831874
      Line 2938, in log /home/runner/_work/pavona/pavona/scratch/main/pwrmgr_top_egret-sim-vcs/33.pwrmgr_stress_all_with_rand_reset/latest/run.log

            Offending 'rstreqs[pwrmgr_reg_pkg::ResetEscIdx]'
        UVM_ERROR @ 1953824235 ps: (pwrmgr_rstreqs_sva_if.sv:88) [ASSERT FAILED] EscRstOn_A
        UVM_INFO @ 1953824235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • ... and 2 more failures.

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 15 failures:

  • Test pwrmgr_disable_rom_integrity_check has 8 failures.

    • 1.pwrmgr_disable_rom_integrity_check.67642940386093528649799305753330421586016329500832707785193926245540649001113
      Line 161, in log /home/runner/_work/pavona/pavona/scratch/main/pwrmgr_top_egret-sim-vcs/1.pwrmgr_disable_rom_integrity_check/latest/run.log

        UVM_FATAL @ 1000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 13.pwrmgr_disable_rom_integrity_check.22760068710268961358324064315184778549510656902166807538965623916334438531502
      Line 118, in log /home/runner/_work/pavona/pavona/scratch/main/pwrmgr_top_egret-sim-vcs/13.pwrmgr_disable_rom_integrity_check/latest/run.log

        UVM_FATAL @ 1000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 6 more failures.

  • Test pwrmgr_reset has 7 failures.

    • 9.pwrmgr_reset.34662134482565945755658832829020828784115511107812056314273925868212446069319
      Line 104, in log /home/runner/_work/pavona/pavona/scratch/main/pwrmgr_top_egret-sim-vcs/9.pwrmgr_reset/latest/run.log

        UVM_FATAL @ 1000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 10.pwrmgr_reset.72765065169646749198829892945997122884269059160129149973074805911185463380929
      Line 82, in log /home/runner/_work/pavona/pavona/scratch/main/pwrmgr_top_egret-sim-vcs/10.pwrmgr_reset/latest/run.log

        UVM_FATAL @ 1000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 5 more failures.

• UVM_FATAL (pwrmgr_reset_vseq.sv:62) [pwrmgr_reset_vseq] wait timeout occurred! has 14 failures:

  • Test pwrmgr_stress_all has 13 failures.

    • 3.pwrmgr_stress_all.12600073850108540557954760542900942212144786096841754265766668740782394854872
      Line 421, in log /home/runner/_work/pavona/pavona/scratch/main/pwrmgr_top_egret-sim-vcs/3.pwrmgr_stress_all/latest/run.log

        UVM_FATAL @ 10525877119 ps: (pwrmgr_reset_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.pwrmgr_reset_vseq] wait timeout occurred!
        UVM_INFO @ 10525877119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 8.pwrmgr_stress_all.98495338755456433873608201802851375425551108118891991820972896993048651935937
      Line 241, in log /home/runner/_work/pavona/pavona/scratch/main/pwrmgr_top_egret-sim-vcs/8.pwrmgr_stress_all/latest/run.log

        UVM_FATAL @ 10356307945 ps: (pwrmgr_reset_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.pwrmgr_reset_vseq] wait timeout occurred!
        UVM_INFO @ 10356307945 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 11 more failures.

  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 41.pwrmgr_stress_all_with_rand_reset.70183428512599162423474832151051467037060863342087824196715310113697205345003
      Line 3366, in log /home/runner/_work/pavona/pavona/scratch/main/pwrmgr_top_egret-sim-vcs/41.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 36013284148 ps: (pwrmgr_reset_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.pwrmgr_reset_vseq] wait timeout occurred!
        UVM_INFO @ 36013284148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:56) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitEnableClocks has 4 failures:

  • Test pwrmgr_reset_invalid has 4 failures.

    • 4.pwrmgr_reset_invalid.36472406335613402063097593540172314174732998564432656149562261956351099550596
      Line 123, in log /home/runner/_work/pavona/pavona/scratch/main/pwrmgr_top_egret-sim-vcs/4.pwrmgr_reset_invalid/latest/run.log

        UVM_FATAL @  69052308 ps: (pwrmgr_reset_invalid_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitEnableClocks
        UVM_INFO @  69052308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 22.pwrmgr_reset_invalid.75163509194390701463852590733541967627257051155618919173453421146547287035245
      Line 96, in log /home/runner/_work/pavona/pavona/scratch/main/pwrmgr_top_egret-sim-vcs/22.pwrmgr_reset_invalid/latest/run.log

        UVM_FATAL @  70407473 ps: (pwrmgr_reset_invalid_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitEnableClocks
        UVM_INFO @  70407473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 2 more failures.

• UVM_FATAL (cip_base_vseq.sv:454) [pwrmgr_common_vseq] wait timeout occurred! has 1 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 1.pwrmgr_stress_all_with_rand_reset.64056345159243922306010012762677461995075839868383128543846164753518267204228
      Line 1781, in log /home/runner/_work/pavona/pavona/scratch/main/pwrmgr_top_egret-sim-vcs/1.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 12640011310 ps: (cip_base_vseq.sv:454) [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] wait timeout occurred!
        UVM_INFO @ 12640011310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:56) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitDisClks has 1 failures:

  • Test pwrmgr_reset_invalid has 1 failures.

    • 26.pwrmgr_reset_invalid.14609822019855883166005321158503278589829770214618540403546457655066304273932
      Line 99, in log /home/runner/_work/pavona/pavona/scratch/main/pwrmgr_top_egret-sim-vcs/26.pwrmgr_reset_invalid/latest/run.log

        UVM_FATAL @  26688333 ps: (pwrmgr_reset_invalid_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitDisClks
        UVM_INFO @  26688333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:56) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitReleaseLcRst has 1 failures:

  • Test pwrmgr_reset_invalid has 1 failures.

    • 27.pwrmgr_reset_invalid.13425195054295094282863684111882575862766752620494323241319233792800246363983
      Line 102, in log /home/runner/_work/pavona/pavona/scratch/main/pwrmgr_top_egret-sim-vcs/27.pwrmgr_reset_invalid/latest/run.log

        UVM_FATAL @  85335075 ps: (pwrmgr_reset_invalid_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitReleaseLcRst
        UVM_INFO @  85335075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1150) [pwrmgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 32.pwrmgr_stress_all_with_rand_reset.15530353702849950979586342432066845630812365653028144915139302362729969353236
      Line 1843, in log /home/runner/_work/pavona/pavona/scratch/main/pwrmgr_top_egret-sim-vcs/32.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7508829412 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 7508829412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:56) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitOtpInit has 1 failures:

  • Test pwrmgr_reset_invalid has 1 failures.

    • 45.pwrmgr_reset_invalid.88988973324011740293710231915351062790913631784949081336803198203557585268345
      Line 128, in log /home/runner/_work/pavona/pavona/scratch/main/pwrmgr_top_egret-sim-vcs/45.pwrmgr_reset_invalid/latest/run.log

        UVM_FATAL @  72414371 ps: (pwrmgr_reset_invalid_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitOtpInit
        UVM_INFO @  72414371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:56) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitLowPower has 1 failures:

  • Test pwrmgr_reset_invalid has 1 failures.

    • 47.pwrmgr_reset_invalid.82099112526368772302223411316583941218397355611254741468533372630827529961708
      Line 120, in log /home/runner/_work/pavona/pavona/scratch/main/pwrmgr_top_egret-sim-vcs/47.pwrmgr_reset_invalid/latest/run.log

        UVM_FATAL @  59509808 ps: (pwrmgr_reset_invalid_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitLowPower
        UVM_INFO @  59509808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:56) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitNvmShutDown has 1 failures:

  • Test pwrmgr_reset_invalid has 1 failures.

    • 49.pwrmgr_reset_invalid.21780141743074033063686142347162328475276419359590423287370082825620011607771
      Line 99, in log /home/runner/_work/pavona/pavona/scratch/main/pwrmgr_top_egret-sim-vcs/49.pwrmgr_reset_invalid/latest/run.log

        UVM_FATAL @  34086764 ps: (pwrmgr_reset_invalid_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitNvmShutDown
        UVM_INFO @  34086764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---