285e653a0b| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | racl_ctrl_smoke | 0 | 50 | 0.00 | ||
| V1 | csr_hw_reset | racl_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | csr_rw | racl_ctrl_csr_rw | 0 | 20 | 0.00 | ||
| V1 | csr_bit_bash | racl_ctrl_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | csr_aliasing | racl_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | racl_ctrl_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | racl_ctrl_csr_rw | 0 | 20 | 0.00 | ||
| racl_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
| V1 | TOTAL | 0 | 105 | 0.00 | |||
| V2 | error_log | error_log | 0 | 0 | -- | ||
| V2 | alert_test | racl_ctrl_alert_test | 0 | 50 | 0.00 | ||
| V2 | intr_test | racl_ctrl_intr_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | racl_ctrl_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_illegal_access | racl_ctrl_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_outstanding_access | racl_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
| racl_ctrl_csr_rw | 0 | 20 | 0.00 | ||||
| racl_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
| racl_ctrl_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | tl_d_partial_access | racl_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
| racl_ctrl_csr_rw | 0 | 20 | 0.00 | ||||
| racl_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
| racl_ctrl_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | TOTAL | 0 | 140 | 0.00 | |||
| V2S | tl_intg_err | racl_ctrl_tl_intg_err | 0 | 20 | 0.00 | ||
| racl_ctrl_sec_cm | 0 | 0 | -- | ||||
| V2S | TOTAL | 0 | 20 | 0.00 | |||
| V3 | stress_all_with_rand_reset | racl_ctrl_stress_all_with_rand_reset | 0 | 50 | 0.00 | ||
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| Unmapped tests | racl_ctrl_stress_all | 0 | 50 | 0.00 | |||
| TOTAL | 0 | 365 | 0.00 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 0 | 0.00 |
| V1 | 6 | 6 | 0 | 0.00 |
| V2 | 5 | 4 | 0 | 0.00 |
| V2S | 2 | 1 | 0 | 0.00 |
| V3 | 1 | 1 | 0 | 0.00 |
Job killed most likely because its dependent job failed. has 367 failures:
0.racl_ctrl_smoke.110686298084229068248334891052166246505819408298944644651327471894314242947459
Log /home/runner/_work/pavona/pavona/scratch/main/racl_ctrl_top_dragonfly-sim-vcs/0.racl_ctrl_smoke/latest/run.log
1.racl_ctrl_smoke.10062449457605959140544568043102587930396224596911964852726580408717508062067
Log /home/runner/_work/pavona/pavona/scratch/main/racl_ctrl_top_dragonfly-sim-vcs/1.racl_ctrl_smoke/latest/run.log
... and 48 more failures.
0.racl_ctrl_stress_all_with_rand_reset.67265836933675991406794103619541376223672908448417125155567451391544815923058
Log /home/runner/_work/pavona/pavona/scratch/main/racl_ctrl_top_dragonfly-sim-vcs/0.racl_ctrl_stress_all_with_rand_reset/latest/run.log
1.racl_ctrl_stress_all_with_rand_reset.16990349450529811380186215316773743632731954445821695417728024418350999615922
Log /home/runner/_work/pavona/pavona/scratch/main/racl_ctrl_top_dragonfly-sim-vcs/1.racl_ctrl_stress_all_with_rand_reset/latest/run.log
... and 48 more failures.
0.racl_ctrl_stress_all.4139368839028444574466131277224568827053603223556050439681315393417609051787
Log /home/runner/_work/pavona/pavona/scratch/main/racl_ctrl_top_dragonfly-sim-vcs/0.racl_ctrl_stress_all/latest/run.log
1.racl_ctrl_stress_all.56433440631392331702700676595312028998460485152018151776710217672153911041098
Log /home/runner/_work/pavona/pavona/scratch/main/racl_ctrl_top_dragonfly-sim-vcs/1.racl_ctrl_stress_all/latest/run.log
... and 48 more failures.
0.racl_ctrl_tl_errors.102193149794734639279430120566735077064855613284351200099314762308003469051828
Log /home/runner/_work/pavona/pavona/scratch/main/racl_ctrl_top_dragonfly-sim-vcs/0.racl_ctrl_tl_errors/latest/run.log
1.racl_ctrl_tl_errors.16899093326161423990011667503373912621285303774982082095655495047233249040170
Log /home/runner/_work/pavona/pavona/scratch/main/racl_ctrl_top_dragonfly-sim-vcs/1.racl_ctrl_tl_errors/latest/run.log
... and 18 more failures.
0.racl_ctrl_tl_intg_err.35722038197601528506006470935667839148226796576957680333489171409352196190722
Log /home/runner/_work/pavona/pavona/scratch/main/racl_ctrl_top_dragonfly-sim-vcs/0.racl_ctrl_tl_intg_err/latest/run.log
1.racl_ctrl_tl_intg_err.29760252845435440624080788001990708406531082618197547189295666032007303771994
Log /home/runner/_work/pavona/pavona/scratch/main/racl_ctrl_top_dragonfly-sim-vcs/1.racl_ctrl_tl_intg_err/latest/run.log
... and 18 more failures.
Error-[SUWC] String used in wrong context has 2 failures:
Test default has 1 failures.
default
Line 1598, in log /home/runner/_work/pavona/pavona/scratch/main/racl_ctrl_top_dragonfly-sim-vcs/default/build.log
Error-[SUWC] String used in wrong context
src/lowrisc_dv_racl_ctrl_env_0.1/racl_ctrl_error_arb_predictor.sv, 92
racl_ctrl_env_pkg, "this.get_full_name()"
A string cannot be used as a boolean expression.
Test cover_reg_top has 1 failures.
cover_reg_top
Line 1478, in log /home/runner/_work/pavona/pavona/scratch/main/racl_ctrl_top_dragonfly-sim-vcs/cover_reg_top/build.log
Error-[SUWC] String used in wrong context
src/lowrisc_dv_racl_ctrl_env_0.1/racl_ctrl_error_arb_predictor.sv, 92
racl_ctrl_env_pkg, "this.get_full_name()"
A string cannot be used as a boolean expression.