ROM_CTRL/32KB Simulation Results

Saturday June 06 2026 03:15:30 UTC

GitHub Revision: 285e653a0b

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	7.750s	2.817ms	2	2	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	6.090s	397.748us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	5.220s	544.184us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	4.400s	239.981us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	4.480s	557.213us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	6.160s	1.056ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	5.220s	544.184us	20	20	100.00
		rom_ctrl_csr_aliasing	4.480s	557.213us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	4.690s	164.425us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	4.250s	296.508us	5	5	100.00
V1		TOTAL			67	67	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	6.300s	8.407ms	3	3	100.00
V2	stress_all	rom_ctrl_stress_all	16.580s	7.980ms	3	3	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	8.690s	1.041ms	2	2	100.00
V2	alert_test	rom_ctrl_alert_test	4.400s	255.600us	3	3	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	7.260s	615.564us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	7.260s	615.564us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	6.090s	397.748us	5	5	100.00
		rom_ctrl_csr_rw	5.220s	544.184us	20	20	100.00
		rom_ctrl_csr_aliasing	4.480s	557.213us	5	5	100.00
		rom_ctrl_same_csr_outstanding	4.100s	172.165us	3	3	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	6.090s	397.748us	5	5	100.00
		rom_ctrl_csr_rw	5.220s	544.184us	20	20	100.00
		rom_ctrl_csr_aliasing	4.480s	557.213us	5	5	100.00
		rom_ctrl_same_csr_outstanding	4.100s	172.165us	3	3	100.00
V2		TOTAL			34	34	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	1.280m	9.551ms	3	4	75.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	14.710s	6.613ms	3	3	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.019m	1.153ms	3	3	100.00
		rom_ctrl_tl_intg_err	39.950s	515.952us	6	6	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.019m	1.153ms	3	3	100.00
V2S	prim_count_check	rom_ctrl_sec_cm	3.019m	1.153ms	3	3	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.280m	9.551ms	3	4	75.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.280m	9.551ms	3	4	75.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.280m	9.551ms	3	4	75.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.280m	9.551ms	3	4	75.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.280m	9.551ms	3	4	75.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.019m	1.153ms	3	3	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.019m	1.153ms	3	3	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	7.750s	2.817ms	2	2	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	7.750s	2.817ms	2	2	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	7.750s	2.817ms	2	2	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	39.950s	515.952us	6	6	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.280m	9.551ms	3	4	75.00
		rom_ctrl_kmac_err_chk	8.690s	1.041ms	2	2	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	1.280m	9.551ms	3	4	75.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.280m	9.551ms	3	4	75.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	1.280m	9.551ms	3	4	75.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	14.710s	6.613ms	3	3	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.019m	1.153ms	3	3	100.00
V2S		TOTAL			15	16	93.75
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	1.325m	6.338ms	4	4	100.00
V3		TOTAL			4	4	100.00
		TOTAL			120	121	99.17

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	3	75.00
V3	1	1	1	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.58	99.59	98.81	95.57	100.00	100.00	96.80	99.28

Failure Buckets

• UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) has 1 failures:
  • Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.

    • 3.rom_ctrl_corrupt_sig_fatal_chk.96665302793339625109325685786772240260249153415514781230741798418746058701941
      Line 103, in log /home/runner/_work/pavona/pavona/scratch/main/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 2313781522 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 2313781522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---