ROM_CTRL/64KB Simulation Results

Saturday June 06 2026 03:15:30 UTC

GitHub Revision: 285e653a0b

Branch: main

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 8.270s 552.222us 2 2 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 10.770s 305.519us 5 5 100.00
V1 csr_rw rom_ctrl_csr_rw 8.230s 1.028ms 20 20 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 8.230s 295.141us 5 5 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 7.910s 301.792us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 8.730s 1.149ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 8.230s 1.028ms 20 20 100.00
rom_ctrl_csr_aliasing 7.910s 301.792us 5 5 100.00
V1 mem_walk rom_ctrl_mem_walk 7.140s 363.852us 5 5 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 7.450s 3.959ms 5 5 100.00
V1 TOTAL 67 67 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 9.710s 1.095ms 2 2 100.00
V2 stress_all rom_ctrl_stress_all 25.980s 8.417ms 4 4 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 13.830s 545.713us 2 2 100.00
V2 alert_test rom_ctrl_alert_test 8.990s 1.999ms 3 3 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 10.080s 658.529us 20 20 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 10.080s 658.529us 20 20 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 10.770s 305.519us 5 5 100.00
rom_ctrl_csr_rw 8.230s 1.028ms 20 20 100.00
rom_ctrl_csr_aliasing 7.910s 301.792us 5 5 100.00
rom_ctrl_same_csr_outstanding 8.840s 319.131us 20 20 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 10.770s 305.519us 5 5 100.00
rom_ctrl_csr_rw 8.230s 1.028ms 20 20 100.00
rom_ctrl_csr_aliasing 7.910s 301.792us 5 5 100.00
rom_ctrl_same_csr_outstanding 8.840s 319.131us 20 20 100.00
V2 TOTAL 51 51 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 2.234m 5.171ms 4 4 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 39.920s 1.570ms 4 4 100.00
V2S tl_intg_err rom_ctrl_sec_cm 5.994m 1.356ms 3 3 100.00
rom_ctrl_tl_intg_err 1.462m 1.123ms 6 6 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 5.994m 1.356ms 3 3 100.00
V2S prim_count_check rom_ctrl_sec_cm 5.994m 1.356ms 3 3 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 2.234m 5.171ms 4 4 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 2.234m 5.171ms 4 4 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 2.234m 5.171ms 4 4 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 2.234m 5.171ms 4 4 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 2.234m 5.171ms 4 4 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 5.994m 1.356ms 3 3 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 5.994m 1.356ms 3 3 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 8.270s 552.222us 2 2 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 8.270s 552.222us 2 2 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 8.270s 552.222us 2 2 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 1.462m 1.123ms 6 6 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 2.234m 5.171ms 4 4 100.00
rom_ctrl_kmac_err_chk 13.830s 545.713us 2 2 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 2.234m 5.171ms 4 4 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 2.234m 5.171ms 4 4 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 2.234m 5.171ms 4 4 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 39.920s 1.570ms 4 4 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 5.994m 1.356ms 3 3 100.00
V2S TOTAL 17 17 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 1.863m 13.188ms 4 4 100.00
V3 TOTAL 4 4 100.00
TOTAL 139 139 100.00

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 6 6 6 100.00
V2S 4 4 4 100.00
V3 1 1 1 100.00

Coverage Results

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.58 99.59 98.81 95.57 100.00 100.00 96.80 99.28