RSTMGR/DRAGONFLY Simulation Results

Saturday June 06 2026 03:15:30 UTC

GitHub Revision: 285e653a0b

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rstmgr_smoke	1.320s	62.054us	50	50	100.00
V1	csr_hw_reset	rstmgr_csr_hw_reset	1.040s	93.943us	5	5	100.00
V1	csr_rw	rstmgr_csr_rw	0.810s	36.289us	20	20	100.00
V1	csr_bit_bash	rstmgr_csr_bit_bash	2.920s	196.194us	5	5	100.00
V1	csr_aliasing	rstmgr_csr_aliasing	0.960s	53.884us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rstmgr_csr_mem_rw_with_rand_reset	1.540s	96.800us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rstmgr_csr_rw	0.810s	36.289us	20	20	100.00
		rstmgr_csr_aliasing	0.960s	53.884us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	reset_stretcher	rstmgr_por_stretcher	1.410s	186.534us	50	50	100.00
V2	sw_rst	rstmgr_sw_rst	1.190s	61.354us	50	50	100.00
V2	sw_rst_reset_race	rstmgr_sw_rst_reset_race	1.300s	91.470us	50	50	100.00
V2	reset_info	rstmgr_reset	5.120s	556.380us	50	50	100.00
V2	cpu_info	rstmgr_reset	5.120s	556.380us	50	50	100.00
V2	alert_info	rstmgr_reset	5.120s	556.380us	50	50	100.00
V2	reset_info_capture	rstmgr_reset	5.120s	556.380us	50	50	100.00
V2	stress_all	rstmgr_stress_all	34.050s	7.116ms	50	50	100.00
V2	alert_test	rstmgr_alert_test	1.420s	83.463us	50	50	100.00
V2	tl_d_oob_addr_access	rstmgr_tl_errors	1.880s	81.412us	20	20	100.00
V2	tl_d_illegal_access	rstmgr_tl_errors	1.880s	81.412us	20	20	100.00
V2	tl_d_outstanding_access	rstmgr_csr_hw_reset	1.040s	93.943us	5	5	100.00
		rstmgr_csr_rw	0.810s	36.289us	20	20	100.00
		rstmgr_csr_aliasing	0.960s	53.884us	5	5	100.00
		rstmgr_same_csr_outstanding	1.070s	71.834us	20	20	100.00
V2	tl_d_partial_access	rstmgr_csr_hw_reset	1.040s	93.943us	5	5	100.00
		rstmgr_csr_rw	0.810s	36.289us	20	20	100.00
		rstmgr_csr_aliasing	0.960s	53.884us	5	5	100.00
		rstmgr_same_csr_outstanding	1.070s	71.834us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	rstmgr_sec_cm	25.710s	6.927ms	5	5	100.00
		rstmgr_tl_intg_err	5.020s	689.634us	20	20	100.00
V2S	prim_count_check	rstmgr_sec_cm	25.710s	6.927ms	5	5	100.00
V2S	prim_fsm_check	rstmgr_sec_cm	25.710s	6.927ms	5	5	100.00
V2S	sec_cm_bus_integrity	rstmgr_tl_intg_err	5.020s	689.634us	20	20	100.00
V2S	sec_cm_scan_intersig_mubi	rstmgr_sec_cm_scan_intersig_mubi	1.310s	68.200us	50	50	100.00
V2S	sec_cm_leaf_rst_bkgn_chk	rstmgr_leaf_rst_cnsty	4.150s	459.264us	48	50	96.00
V2S	sec_cm_leaf_rst_shadow	rstmgr_leaf_rst_shadow_attack	1.860s	291.187us	50	50	100.00
V2S	sec_cm_leaf_fsm_sparse	rstmgr_sec_cm	25.710s	6.927ms	5	5	100.00
V2S	sec_cm_sw_rst_config_regwen	rstmgr_csr_rw	0.810s	36.289us	20	20	100.00
V2S	sec_cm_dump_ctrl_config_regwen	rstmgr_csr_rw	0.810s	36.289us	20	20	100.00
V2S		TOTAL			173	175	98.86
V3	stress_all_with_rand_reset	rstmgr_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			618	620	99.68

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	5	5	4	80.00
V3	1	0	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.08	99.19	99.43	100.00	--	99.72	97.62	98.49

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert fatal_cnsty_fault did not trigger max_delay:* has 2 failures:
  • Test rstmgr_leaf_rst_cnsty has 2 failures.

    • 31.rstmgr_leaf_rst_cnsty.39864166837016678625160822448800099627756419803650185764352008133474347377661
      Line 128, in log /home/runner/_work/pavona/pavona/scratch/main/rstmgr_top_dragonfly-sim-vcs/31.rstmgr_leaf_rst_cnsty/latest/run.log

        UVM_ERROR @ 219325995 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_cnsty_fault did not trigger max_delay:20
        UVM_INFO @ 219325995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 41.rstmgr_leaf_rst_cnsty.26558142947971165604603728768442035758625150566390034735601226815516470112798
      Line 88, in log /home/runner/_work/pavona/pavona/scratch/main/rstmgr_top_dragonfly-sim-vcs/41.rstmgr_leaf_rst_cnsty/latest/run.log

        UVM_ERROR @  61450452 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_cnsty_fault did not trigger max_delay:20
        UVM_INFO @  61450452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---