RSTMGR/EGRET Simulation Results

Saturday June 06 2026 03:15:30 UTC

GitHub Revision: 285e653a0b

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rstmgr_smoke	1.230s	229.317us	50	50	100.00
V1	csr_hw_reset	rstmgr_csr_hw_reset	0.660s	144.447us	5	5	100.00
V1	csr_rw	rstmgr_csr_rw	0.720s	89.108us	20	20	100.00
V1	csr_bit_bash	rstmgr_csr_bit_bash	4.950s	1.559ms	5	5	100.00
V1	csr_aliasing	rstmgr_csr_aliasing	1.540s	353.161us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rstmgr_csr_mem_rw_with_rand_reset	1.040s	186.454us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rstmgr_csr_rw	0.720s	89.108us	20	20	100.00
		rstmgr_csr_aliasing	1.540s	353.161us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	reset_stretcher	rstmgr_por_stretcher	0.960s	193.903us	50	50	100.00
V2	sw_rst	rstmgr_sw_rst	1.860s	554.579us	50	50	100.00
V2	sw_rst_reset_race	rstmgr_sw_rst_reset_race	1.150s	191.165us	50	50	100.00
V2	reset_info	rstmgr_reset	4.990s	2.177ms	50	50	100.00
V2	cpu_info	rstmgr_reset	4.990s	2.177ms	50	50	100.00
V2	alert_info	rstmgr_reset	4.990s	2.177ms	50	50	100.00
V2	reset_info_capture	rstmgr_reset	4.990s	2.177ms	50	50	100.00
V2	stress_all	rstmgr_stress_all	29.200s	15.132ms	50	50	100.00
V2	alert_test	rstmgr_alert_test	0.760s	69.151us	50	50	100.00
V2	tl_d_oob_addr_access	rstmgr_tl_errors	2.310s	635.994us	20	20	100.00
V2	tl_d_illegal_access	rstmgr_tl_errors	2.310s	635.994us	20	20	100.00
V2	tl_d_outstanding_access	rstmgr_csr_hw_reset	0.660s	144.447us	5	5	100.00
		rstmgr_csr_rw	0.720s	89.108us	20	20	100.00
		rstmgr_csr_aliasing	1.540s	353.161us	5	5	100.00
		rstmgr_same_csr_outstanding	1.080s	237.451us	20	20	100.00
V2	tl_d_partial_access	rstmgr_csr_hw_reset	0.660s	144.447us	5	5	100.00
		rstmgr_csr_rw	0.720s	89.108us	20	20	100.00
		rstmgr_csr_aliasing	1.540s	353.161us	5	5	100.00
		rstmgr_same_csr_outstanding	1.080s	237.451us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	rstmgr_sec_cm	18.360s	16.827ms	5	5	100.00
		rstmgr_tl_intg_err	3.920s	2.879ms	20	20	100.00
V2S	prim_count_check	rstmgr_sec_cm	18.360s	16.827ms	5	5	100.00
V2S	prim_fsm_check	rstmgr_sec_cm	18.360s	16.827ms	5	5	100.00
V2S	sec_cm_bus_integrity	rstmgr_tl_intg_err	3.920s	2.879ms	20	20	100.00
V2S	sec_cm_scan_intersig_mubi	rstmgr_sec_cm_scan_intersig_mubi	0.970s	191.073us	50	50	100.00
V2S	sec_cm_leaf_rst_bkgn_chk	rstmgr_leaf_rst_cnsty	5.850s	2.460ms	50	50	100.00
V2S	sec_cm_leaf_rst_shadow	rstmgr_leaf_rst_shadow_attack	0.980s	302.076us	50	50	100.00
V2S	sec_cm_leaf_fsm_sparse	rstmgr_sec_cm	18.360s	16.827ms	5	5	100.00
V2S	sec_cm_sw_rst_config_regwen	rstmgr_csr_rw	0.720s	89.108us	20	20	100.00
V2S	sec_cm_dump_ctrl_config_regwen	rstmgr_csr_rw	0.720s	89.108us	20	20	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	rstmgr_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			620	620	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	5	5	5	100.00
V3	1	0	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.27	99.51	99.38	100.00	--	99.83	98.13	98.76