285e653a0b| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rv_dm_smoke | 1.120s | 1.489ms | 2 | 2 | 100.00 |
| V1 | jtag_dtm_csr_hw_reset | rv_dm_jtag_dtm_csr_hw_reset | 1.730s | 711.011us | 5 | 5 | 100.00 |
| V1 | jtag_dtm_csr_rw | rv_dm_jtag_dtm_csr_rw | 1.540s | 523.763us | 20 | 20 | 100.00 |
| V1 | jtag_dtm_csr_bit_bash | rv_dm_jtag_dtm_csr_bit_bash | 16.460s | 16.624ms | 5 | 5 | 100.00 |
| V1 | jtag_dtm_csr_aliasing | rv_dm_jtag_dtm_csr_aliasing | 1.930s | 778.113us | 5 | 5 | 100.00 |
| V1 | jtag_dmi_csr_hw_reset | rv_dm_jtag_dmi_csr_hw_reset | 19.990s | 13.619ms | 5 | 5 | 100.00 |
| V1 | jtag_dmi_csr_rw | rv_dm_jtag_dmi_csr_rw | 17.100s | 10.531ms | 20 | 20 | 100.00 |
| V1 | jtag_dmi_csr_bit_bash | rv_dm_jtag_dmi_csr_bit_bash | 1.485m | 65.535ms | 20 | 20 | 100.00 |
| V1 | jtag_dmi_csr_aliasing | rv_dm_jtag_dmi_csr_aliasing | 1.774m | 70.670ms | 5 | 5 | 100.00 |
| V1 | jtag_dmi_cmderr_busy | rv_dm_cmderr_busy | 1.350s | 1.154ms | 2 | 2 | 100.00 |
| V1 | jtag_dmi_cmderr_not_supported | rv_dm_cmderr_not_supported | 0.910s | 781.707us | 2 | 2 | 100.00 |
| V1 | cmderr_exception | rv_dm_cmderr_exception | 0.770s | 170.412us | 2 | 2 | 100.00 |
| V1 | mem_tl_access_resuming | rv_dm_mem_tl_access_resuming | 0.560s | 149.916us | 0 | 2 | 0.00 |
| V1 | mem_tl_access_halted | rv_dm_mem_tl_access_halted | 0.620s | 194.529us | 2 | 2 | 100.00 |
| V1 | cmderr_halt_resume | rv_dm_cmderr_halt_resume | 0.870s | 948.319us | 2 | 2 | 100.00 |
| V1 | dataaddr_rw_access | rv_dm_dataaddr_rw_access | 0.750s | 314.758us | 2 | 2 | 100.00 |
| V1 | halt_resume | rv_dm_halt_resume_whereto | 3.910s | 1.376ms | 8 | 8 | 100.00 |
| V1 | progbuf_busy | rv_dm_cmderr_busy | 1.350s | 1.154ms | 2 | 2 | 100.00 |
| V1 | abstractcmd_status | rv_dm_abstractcmd_status | 0.700s | 122.343us | 2 | 2 | 100.00 |
| V1 | progbuf_read_write_execute | rv_dm_progbuf_read_write_execute | 2.140s | 1.378ms | 2 | 2 | 100.00 |
| V1 | progbuf_exception | rv_dm_cmderr_exception | 0.770s | 170.412us | 2 | 2 | 100.00 |
| V1 | rom_read_access | rv_dm_rom_read_access | 0.810s | 106.167us | 2 | 2 | 100.00 |
| V1 | csr_hw_reset | rv_dm_csr_hw_reset | 1.520s | 147.927us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_dm_csr_rw | 2.060s | 369.306us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_dm_csr_bit_bash | 39.560s | 20.455ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_dm_csr_aliasing | 41.760s | 4.399ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_dm_csr_mem_rw_with_rand_reset | 3.260s | 486.647us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_dm_csr_aliasing | 41.760s | 4.399ms | 5 | 5 | 100.00 |
| rv_dm_csr_rw | 2.060s | 369.306us | 20 | 20 | 100.00 | ||
| V1 | mem_walk | rv_dm_mem_walk | 0.790s | 165.877us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | rv_dm_mem_partial_access | 0.670s | 131.929us | 5 | 5 | 100.00 |
| V1 | TOTAL | 178 | 180 | 98.89 | |||
| V2 | idcode | rv_dm_smoke | 1.120s | 1.489ms | 2 | 2 | 100.00 |
| V2 | jtag_dtm_hard_reset | rv_dm_jtag_dtm_hard_reset | 1.520s | 705.711us | 2 | 2 | 100.00 |
| V2 | jtag_dtm_idle_hint | rv_dm_jtag_dtm_idle_hint | 0.720s | 510.433us | 2 | 2 | 100.00 |
| V2 | jtag_dmi_failed_op | rv_dm_dmi_failed_op | 1.070s | 341.995us | 2 | 2 | 100.00 |
| V2 | jtag_dmi_dm_inactive | rv_dm_jtag_dmi_dm_inactive | 3.500s | 2.188ms | 2 | 2 | 100.00 |
| V2 | sba | rv_dm_sba_tl_access | 10.152m | 300.000ms | 0 | 20 | 0.00 |
| rv_dm_delayed_resp_sba_tl_access | 8.504m | 300.000ms | 0 | 20 | 0.00 | ||
| V2 | bad_sba | rv_dm_bad_sba_tl_access | 10.768m | 300.000ms | 0 | 20 | 0.00 |
| V2 | sba_autoincrement | rv_dm_autoincr_sba_tl_access | 10.445m | 300.000ms | 0 | 20 | 0.00 |
| V2 | jtag_dmi_debug_disabled | rv_dm_jtag_dmi_debug_disabled | 0.560s | 301.916us | 0 | 2 | 0.00 |
| V2 | sba_debug_disabled | rv_dm_sba_debug_disabled | 4.130s | 2.734ms | 2 | 2 | 100.00 |
| V2 | ndmreset_req | rv_dm_ndmreset_req | 1.370s | 593.344us | 2 | 2 | 100.00 |
| V2 | hart_unavail | rv_dm_hart_unavail | 1.060s | 200.537us | 0 | 5 | 0.00 |
| V2 | tap_ctrl_transitions | rv_dm_tap_fsm | 10.760s | 14.946ms | 1 | 1 | 100.00 |
| rv_dm_tap_fsm_rand_reset | 50.650s | 4.186ms | 10 | 10 | 100.00 | ||
| V2 | hartsel_warl | rv_dm_hartsel_warl | 0.590s | 94.650us | 1 | 1 | 100.00 |
| V2 | stress_all | rv_dm_stress_all | 2.777h | 10.000s | 3 | 50 | 6.00 |
| V2 | alert_test | rv_dm_alert_test | 1.270s | 181.829us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_dm_tl_errors | 3.460s | 414.775us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_dm_tl_errors | 3.460s | 414.775us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_dm_csr_aliasing | 41.760s | 4.399ms | 5 | 5 | 100.00 |
| rv_dm_csr_hw_reset | 1.520s | 147.927us | 5 | 5 | 100.00 | ||
| rv_dm_csr_rw | 2.060s | 369.306us | 20 | 20 | 100.00 | ||
| rv_dm_same_csr_outstanding | 5.000s | 1.160ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_dm_csr_aliasing | 41.760s | 4.399ms | 5 | 5 | 100.00 |
| rv_dm_csr_hw_reset | 1.520s | 147.927us | 5 | 5 | 100.00 | ||
| rv_dm_csr_rw | 2.060s | 369.306us | 20 | 20 | 100.00 | ||
| rv_dm_same_csr_outstanding | 5.000s | 1.160ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 117 | 251 | 46.61 | |||
| V2S | tl_intg_err | rv_dm_sec_cm | 7.670s | 2.773ms | 5 | 5 | 100.00 |
| rv_dm_tl_intg_err | 16.790s | 5.888ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_dm_tl_intg_err | 16.790s | 5.888ms | 20 | 20 | 100.00 |
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | rv_dm_sba_debug_disabled | 4.130s | 2.734ms | 2 | 2 | 100.00 |
| rv_dm_debug_disabled | 0.640s | 117.696us | 1 | 2 | 50.00 | ||
| V2S | sec_cm_lc_hw_debug_clr_intersig_mubi | sec_cm_lc_hw_debug_clr_intersig_mubi | 0 | 0 | -- | ||
| V2S | sec_cm_lc_dft_en_intersig_mubi | rv_dm_sba_debug_disabled | 4.130s | 2.734ms | 2 | 2 | 100.00 |
| rv_dm_debug_disabled | 0.640s | 117.696us | 1 | 2 | 50.00 | ||
| V2S | sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | rv_dm_smoke | 1.120s | 1.489ms | 2 | 2 | 100.00 |
| V2S | sec_cm_dm_en_ctrl_lc_gated | rv_dm_buffered_enable | 1.260s | 505.232us | 10 | 10 | 100.00 |
| V2S | sec_cm_sba_tl_lc_gate_fsm_sparse | rv_dm_sparse_lc_gate_fsm | 1.310s | 188.198us | 4 | 4 | 100.00 |
| V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | rv_dm_sparse_lc_gate_fsm | 1.310s | 188.198us | 4 | 4 | 100.00 |
| V2S | sec_cm_exec_ctrl_mubi | rv_dm_buffered_enable | 1.260s | 505.232us | 10 | 10 | 100.00 |
| V2S | TOTAL | 40 | 41 | 97.56 | |||
| V3 | stress_all_with_rand_reset | rv_dm_stress_all_with_rand_reset | 24.270s | 9.400ms | 0 | 10 | 0.00 |
| V3 | TOTAL | 0 | 10 | 0.00 | |||
| Unmapped tests | rv_dm_scanmode | 1.406m | 300.000ms | 0 | 1 | 0.00 | |
| TOTAL | 335 | 483 | 69.36 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 0 | 0.00 |
| V1 | 27 | 27 | 26 | 96.30 |
| V2 | 19 | 19 | 12 | 63.16 |
| V2S | 6 | 5 | 4 | 66.67 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 74.53 | 90.90 | 78.41 | 65.04 | 56.25 | 76.07 | 96.24 | 58.83 |
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 89 failures:
Test rv_dm_sba_tl_access has 20 failures.
0.rv_dm_sba_tl_access.24130429194597388556447996109334381947623675442373812546689426216841429822685
Line 90, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/0.rv_dm_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_dm_sba_tl_access.49979054028898060338269651532622625844168558247956683405023184218362287785053
Line 90, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/1.rv_dm_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 18 more failures.
Test rv_dm_delayed_resp_sba_tl_access has 20 failures.
0.rv_dm_delayed_resp_sba_tl_access.92612254657029128813712110338136365392050750714718537928206801915886312380712
Line 90, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/0.rv_dm_delayed_resp_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_dm_delayed_resp_sba_tl_access.64443150711143083191811830925905198977214454847631221226047435587254208041953
Line 90, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/1.rv_dm_delayed_resp_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 18 more failures.
Test rv_dm_bad_sba_tl_access has 20 failures.
0.rv_dm_bad_sba_tl_access.6293774964155580295378868931994468229313635430603197725836669652886359656756
Line 90, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/0.rv_dm_bad_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_dm_bad_sba_tl_access.109822455491056601221067505824782779494016474548785349531199877365685028580014
Line 90, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/1.rv_dm_bad_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 18 more failures.
Test rv_dm_autoincr_sba_tl_access has 20 failures.
0.rv_dm_autoincr_sba_tl_access.88152597453024540681788636072991405237446345428789923111435049597288610417944
Line 90, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/0.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_dm_autoincr_sba_tl_access.26973766899523803972433555492929795356186779620697597572707362980130113052566
Line 90, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/1.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 18 more failures.
Test rv_dm_scanmode has 1 failures.
0.rv_dm_scanmode.5020431495837781595702361421455812425183407232289255369277947821580345585817
Line 81, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/0.rv_dm_scanmode/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more tests.
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failedgmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (* [] vs * [])` has 23 failures:
Test rv_dm_hart_unavail has 5 failures.
0.rv_dm_hart_unavail.94312094747190473223203720967099347328366912276534553525066875826739280152710
Line 86, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/0.rv_dm_hart_unavail/latest/run.log
UVM_ERROR @ 274388041 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 274388041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_dm_hart_unavail.26381084321523768114322444766421739288640172862271384389804587985582985540611
Line 86, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/1.rv_dm_hart_unavail/latest/run.log
UVM_ERROR @ 32791133 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 32791133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Test rv_dm_stress_all_with_rand_reset has 2 failures.
0.rv_dm_stress_all_with_rand_reset.27470259646226306947614294841365970641815890818156306625496043928031219205828
Line 97, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1688636878 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1688636878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.rv_dm_stress_all_with_rand_reset.6397541999092807005136850307267837480402680222509728185280860027904404955258
Line 137, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1739299533 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1739299533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all has 16 failures.
2.rv_dm_stress_all.89143163115246535066463688917263620468611453673852824101220660153024393211813
Line 87, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/2.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 105233339 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 105233339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.rv_dm_stress_all.103873713964864555707211355531348568144665904473167866476122750498860959089317
Line 92, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/3.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 5340328301 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 5340328301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 14 more failures.
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failedgmv(jtag_dmi_ral.dmstatus.anyhalted) == 'b (* [] vs * [])` has 19 failures:
Test rv_dm_mem_tl_access_resuming has 2 failures.
0.rv_dm_mem_tl_access_resuming.61292777746715407118724673700144649808897095281269851824810993137591769133271
Line 81, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/0.rv_dm_mem_tl_access_resuming/latest/run.log
UVM_ERROR @ 149916135 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 149916135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_dm_mem_tl_access_resuming.40230299180550810918543155922834059167011357144191080072832437006092575819489
Line 86, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/1.rv_dm_mem_tl_access_resuming/latest/run.log
UVM_ERROR @ 66866065 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 66866065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all has 13 failures.
0.rv_dm_stress_all.52587848228829915618760227912571892434900471418735145325770551731073436122413
Line 85, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/0.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 1643975829 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1643975829 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_dm_stress_all.108922914216807757057420244014035623841935204459996682128674635524291056373689
Line 87, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/1.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 420669554 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 420669554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 11 more failures.
Test rv_dm_stress_all_with_rand_reset has 4 failures.
2.rv_dm_stress_all_with_rand_reset.12394584364067695721976475262945192851739039477252089434156274005487987814107
Line 90, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 146553976 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 146553976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.rv_dm_stress_all_with_rand_reset.26594510657949825005127048195066960065453235436117512440339176276903219372792
Line 130, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1809924318 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1809924318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*]) has 11 failures:
Test rv_dm_jtag_dmi_debug_disabled has 2 failures.
0.rv_dm_jtag_dmi_debug_disabled.43425999612788745334149876462599065829457086146833997210948788947484979326888
Line 81, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/0.rv_dm_jtag_dmi_debug_disabled/latest/run.log
UVM_ERROR @ 301915512 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (1423065145 [0x54d24039] vs 0 [0x0])
UVM_INFO @ 301915512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_dm_jtag_dmi_debug_disabled.73387274215436531770721593167029345932017904129476613395937618041989400973283
Line 81, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/1.rv_dm_jtag_dmi_debug_disabled/latest/run.log
UVM_ERROR @ 123485754 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (3878904497 [0xe73362b1] vs 0 [0x0])
UVM_INFO @ 123485754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all_with_rand_reset has 2 failures.
1.rv_dm_stress_all_with_rand_reset.62133748376143331322350562507638978869063372605275432214884122450730032617344
Line 150, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 9400227627 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (2091345715 [0x7ca76733] vs 0 [0x0])
UVM_INFO @ 9400227627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.rv_dm_stress_all_with_rand_reset.23542368983893103359138412819831585805071345200584106881577508476119454226956
Line 90, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 716937301 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (1595818212 [0x5f1e40e4] vs 0 [0x0])
UVM_INFO @ 716937301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all has 7 failures.
17.rv_dm_stress_all.95947001509233684054647768216409314685196826447671281313453733899114413702779
Line 90, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/17.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 1184221266 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (2124925264 [0x7ea7c950] vs 0 [0x0])
UVM_INFO @ 1184221266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
25.rv_dm_stress_all.102698252509757467860719614093750141593435861539305667844887132162671315905195
Line 90, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/25.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 1324288740 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (2622817657 [0x9c550579] vs 0 [0x0])
UVM_INFO @ 1324288740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
Job timed out after * minutes has 3 failures:
10.rv_dm_stress_all.12284591448419951042918263211048108552855437062664498669709339248713262258615
Log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/10.rv_dm_stress_all/latest/run.log
Job timed out after 180 minutes
23.rv_dm_stress_all.12040831296661774258281322149912721460766560188812095528336444938519915611625
Log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/23.rv_dm_stress_all/latest/run.log
Job timed out after 180 minutes
... and 1 more failures.
UVM_FATAL (cip_base_vseq.sv:1171) [rv_dm_common_vseq] Check failed (vseq_done) has 2 failures:
4.rv_dm_stress_all_with_rand_reset.864767958492068620962785404777943637935310147959644872468950468075074456635
Line 113, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 696330224 ps: (cip_base_vseq.sv:1171) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (vseq_done)
UVM_INFO @ 696330224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.rv_dm_stress_all_with_rand_reset.85226258850029539030211770223502955784854375578860635922437995015198471263516
Line 107, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/9.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 882794340 ps: (cip_base_vseq.sv:1171) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (vseq_done)
UVM_INFO @ 882794340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_debug_disabled_vseq.sv:33) [rv_dm_debug_disabled_vseq] Check failed (rvalue == expected_output) has 1 failures:
0.rv_dm_debug_disabled.3225886657853167673363002848724725786277681035087420312384867454625425959432
Line 85, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/0.rv_dm_debug_disabled/latest/run.log
UVM_ERROR @ 117696168 ps: (rv_dm_debug_disabled_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.rv_dm_debug_disabled_vseq] Check failed (rvalue == expected_output)
UVM_INFO @ 117696168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---