RV_DM/USE_JTAG_INTERFACE Simulation Results

Saturday June 06 2026 03:15:30 UTC

GitHub Revision: 285e653a0b

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	1.460s	1.262ms	2	2	100.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	1.380s	368.751us	5	5	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	2.620s	948.512us	20	20	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	1.248m	41.998ms	5	5	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	2.470s	554.347us	5	5	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	14.990s	9.233ms	5	5	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	24.710s	8.901ms	20	20	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	2.817m	93.086ms	20	20	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	2.734m	96.325ms	5	5	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	1.280s	488.075us	2	2	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	0.770s	167.071us	2	2	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	1.730s	805.176us	2	2	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	1.830s	880.145us	2	2	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	0.640s	144.512us	2	2	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	1.320s	1.289ms	2	2	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	0.650s	254.782us	2	2	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	2.860s	1.161ms	8	8	100.00
V1	progbuf_busy	rv_dm_cmderr_busy	1.280s	488.075us	2	2	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	1.250s	519.725us	2	2	100.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	0.830s	234.058us	2	2	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	1.730s	805.176us	2	2	100.00
V1	rom_read_access	rv_dm_rom_read_access	0.660s	371.500us	2	2	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	2.570s	568.700us	5	5	100.00
V1	csr_rw	rv_dm_csr_rw	2.170s	146.681us	20	20	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	45.860s	22.931ms	5	5	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	41.010s	3.508ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	2.440s	121.681us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	41.010s	3.508ms	5	5	100.00
		rv_dm_csr_rw	2.170s	146.681us	20	20	100.00
V1	mem_walk	rv_dm_mem_walk	0.850s	83.576us	5	5	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	0.900s	81.098us	5	5	100.00
V1		TOTAL			180	180	100.00
V2	idcode	rv_dm_smoke	1.460s	1.262ms	2	2	100.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	0.980s	692.314us	2	2	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	0.570s	149.711us	2	2	100.00
V2	jtag_dmi_failed_op	rv_dm_dmi_failed_op	1.230s	483.535us	2	2	100.00
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	1.850s	973.919us	2	2	100.00
V2	sba	rv_dm_sba_tl_access	11.096m	300.000ms	0	20	0.00
		rv_dm_delayed_resp_sba_tl_access	9.086m	300.000ms	0	20	0.00
V2	bad_sba	rv_dm_bad_sba_tl_access	9.839m	300.000ms	0	20	0.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	8.981m	300.000ms	0	20	0.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	1.330s	584.931us	2	2	100.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	3.700s	4.486ms	2	2	100.00
V2	ndmreset_req	rv_dm_ndmreset_req	1.620s	777.181us	2	2	100.00
V2	hart_unavail	rv_dm_hart_unavail	1.120s	150.857us	5	5	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	2.150s	3.572ms	1	1	100.00
		rv_dm_tap_fsm_rand_reset	47.390s	3.628ms	10	10	100.00
V2	hartsel_warl	rv_dm_hartsel_warl	0.640s	218.892us	1	1	100.00
V2	stress_all	rv_dm_stress_all	15.040s	5.493ms	50	50	100.00
V2	alert_test	rv_dm_alert_test	1.180s	129.497us	50	50	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	4.180s	475.037us	20	20	100.00
V2	tl_d_illegal_access	rv_dm_tl_errors	4.180s	475.037us	20	20	100.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	41.010s	3.508ms	5	5	100.00
		rv_dm_csr_hw_reset	2.570s	568.700us	5	5	100.00
		rv_dm_csr_rw	2.170s	146.681us	20	20	100.00
		rv_dm_same_csr_outstanding	6.260s	852.227us	20	20	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	41.010s	3.508ms	5	5	100.00
		rv_dm_csr_hw_reset	2.570s	568.700us	5	5	100.00
		rv_dm_csr_rw	2.170s	146.681us	20	20	100.00
		rv_dm_same_csr_outstanding	6.260s	852.227us	20	20	100.00
V2		TOTAL			171	251	68.13
V2S	tl_intg_err	rv_dm_sec_cm	4.290s	2.569ms	5	5	100.00
		rv_dm_tl_intg_err	16.000s	6.417ms	20	20	100.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	16.000s	6.417ms	20	20	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	3.700s	4.486ms	2	2	100.00
		rv_dm_debug_disabled	0.730s	159.683us	1	2	50.00
V2S	sec_cm_lc_hw_debug_clr_intersig_mubi	sec_cm_lc_hw_debug_clr_intersig_mubi			0	0	--
V2S	sec_cm_lc_dft_en_intersig_mubi	rv_dm_sba_debug_disabled	3.700s	4.486ms	2	2	100.00
		rv_dm_debug_disabled	0.730s	159.683us	1	2	50.00
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	rv_dm_smoke	1.460s	1.262ms	2	2	100.00
V2S	sec_cm_dm_en_ctrl_lc_gated	rv_dm_buffered_enable	2.030s	438.717us	10	10	100.00
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	1.140s	252.259us	4	4	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	1.140s	252.259us	4	4	100.00
V2S	sec_cm_exec_ctrl_mubi	rv_dm_buffered_enable	2.030s	438.717us	10	10	100.00
V2S		TOTAL			40	41	97.56
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	1.326m	5.727ms	10	10	100.00
V3		TOTAL			10	10	100.00
	Unmapped tests	rv_dm_scanmode	0.500s	26.343us	1	1	100.00
		TOTAL			402	483	83.23

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	27	27	27	100.00
V2	19	19	15	78.95
V2S	6	5	4	66.67
V3	1	1	1	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
80.00	95.84	90.15	68.86	89.61	88.97	95.39	31.18

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 80 failures:
  • Test rv_dm_sba_tl_access has 20 failures.

    • 0.rv_dm_sba_tl_access.22118447930311273150696588471363894233958240843281601513487305385757304908623
      Line 90, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_jtag_interface-sim-vcs/0.rv_dm_sba_tl_access/latest/run.log

        UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.rv_dm_sba_tl_access.28133606489571199300136083883612478501474345956116505352385388647665101150984
      Line 90, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_jtag_interface-sim-vcs/1.rv_dm_sba_tl_access/latest/run.log

        UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 18 more failures.

  • Test rv_dm_delayed_resp_sba_tl_access has 20 failures.

    • 0.rv_dm_delayed_resp_sba_tl_access.46162365676636285877909558616464095728535394140428147681806943641522357764051
      Line 90, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_jtag_interface-sim-vcs/0.rv_dm_delayed_resp_sba_tl_access/latest/run.log

        UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.rv_dm_delayed_resp_sba_tl_access.112548451886648154602462380245003749376767372652992820476185313269275146141903
      Line 90, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_jtag_interface-sim-vcs/1.rv_dm_delayed_resp_sba_tl_access/latest/run.log

        UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 18 more failures.

  • Test rv_dm_bad_sba_tl_access has 20 failures.

    • 0.rv_dm_bad_sba_tl_access.76186916097118260780565099867785088176438379276295240911606761128694591232388
      Line 90, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_jtag_interface-sim-vcs/0.rv_dm_bad_sba_tl_access/latest/run.log

        UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.rv_dm_bad_sba_tl_access.68918070392059556445108434316189004189975826284821502175510634487006088732841
      Line 90, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_jtag_interface-sim-vcs/1.rv_dm_bad_sba_tl_access/latest/run.log

        UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 18 more failures.

  • Test rv_dm_autoincr_sba_tl_access has 20 failures.

    • 0.rv_dm_autoincr_sba_tl_access.33024333614961941544233092773106646511680676651872058767255504783458870226539
      Line 90, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_jtag_interface-sim-vcs/0.rv_dm_autoincr_sba_tl_access/latest/run.log

        UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.rv_dm_autoincr_sba_tl_access.85209032101491566578837817926261038173053742053911107724321344954160520868100
      Line 90, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_jtag_interface-sim-vcs/1.rv_dm_autoincr_sba_tl_access/latest/run.log

        UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 18 more failures.

• UVM_ERROR (rv_dm_debug_disabled_vseq.sv:33) [rv_dm_debug_disabled_vseq] Check failed (rvalue == expected_output) has 1 failures:
  • Test rv_dm_debug_disabled has 1 failures.

    • 1.rv_dm_debug_disabled.54431881958380436512247375346230342103856440161129702210222987254731371067398
      Line 89, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_jtag_interface-sim-vcs/1.rv_dm_debug_disabled/latest/run.log

        UVM_ERROR @ 159682620 ps: (rv_dm_debug_disabled_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.rv_dm_debug_disabled_vseq] Check failed (rvalue == expected_output)
        UVM_INFO @ 159682620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---