285e653a0b| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 2.050s | 902.860us | 20 | 20 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.660s | 15.296us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.560s | 34.365us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 2.010s | 283.899us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.730s | 554.590us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 0.920s | 33.937us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.560s | 34.365us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 0.730s | 554.590us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 75 | 75 | 100.00 | |||
| V2 | random_reset | rv_timer_random_reset | 11.220s | 6.883ms | 1 | 20 | 5.00 |
| V2 | disabled | rv_timer_disabled | 3.100s | 2.070ms | 20 | 20 | 100.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 5.877m | 649.011ms | 10 | 10 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 5.877m | 649.011ms | 10 | 10 | 100.00 |
| V2 | stress | rv_timer_stress_all | 8.760s | 6.853ms | 20 | 20 | 100.00 |
| V2 | alert_test | rv_timer_alert_test | 0.690s | 41.168us | 50 | 50 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.550s | 75.816us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 1.840s | 191.104us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 1.840s | 191.104us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.660s | 15.296us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.560s | 34.365us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.730s | 554.590us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.690s | 76.913us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.660s | 15.296us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.560s | 34.365us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.730s | 554.590us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.690s | 76.913us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 191 | 210 | 90.95 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 0.960s | 317.706us | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 1.200s | 1.223ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.200s | 1.223ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | min_value | rv_timer_min | 1.420s | 804.776us | 1 | 10 | 10.00 |
| V3 | max_value | rv_timer_max | 0.710s | 173.570us | 1 | 10 | 10.00 |
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 41.320s | 5.640ms | 16 | 20 | 80.00 |
| V3 | TOTAL | 18 | 40 | 45.00 | |||
| TOTAL | 309 | 350 | 88.29 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 8 | 8 | 7 | 87.50 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 3 | 3 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.47 | 100.00 | 100.00 | 100.00 | -- | 100.00 | 96.82 | 100.00 |
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 28 failures:
0.rv_timer_min.41252331726986355853286187365799606037106392211147240883012463366110402733169
Line 77, in log /home/runner/_work/pavona/pavona/scratch/main/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log
UVM_FATAL @ 127421866 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x6d97d904) == 0x1
UVM_INFO @ 127421866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_timer_min.11739543318545821518890340967695012284105142276518945299414118427363634373116
Line 77, in log /home/runner/_work/pavona/pavona/scratch/main/rv_timer-sim-vcs/1.rv_timer_min/latest/run.log
UVM_FATAL @ 59179449 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x9d4304) == 0x1
UVM_INFO @ 59179449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
0.rv_timer_random_reset.28767276902557733009543636294023264536108065599881360141867439231256543535716
Line 77, in log /home/runner/_work/pavona/pavona/scratch/main/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log
UVM_FATAL @ 745511828 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x84140104) == 0x1
UVM_INFO @ 745511828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_timer_random_reset.45733387735629124764116925219397294742426636408117957883308725477845606983875
Line 78, in log /home/runner/_work/pavona/pavona/scratch/main/rv_timer-sim-vcs/1.rv_timer_random_reset/latest/run.log
UVM_FATAL @ 204629814 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x1d04904) == 0x1
UVM_INFO @ 204629814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 17 more failures.
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 8 failures:
0.rv_timer_max.93834510718241473993462638164493881659111276900274495013827386052714926449835
Line 77, in log /home/runner/_work/pavona/pavona/scratch/main/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log
UVM_ERROR @ 106451381 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 106451381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.rv_timer_max.100128084295555637064159827602217416367274354972533843293302489580006668421410
Line 77, in log /home/runner/_work/pavona/pavona/scratch/main/rv_timer-sim-vcs/2.rv_timer_max/latest/run.log
UVM_ERROR @ 424423086 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 424423086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 2 failures:
2.rv_timer_stress_all_with_rand_reset.1847820460433302881982616774794384933511968234670752685751264275308441147108
Line 132, in log /home/runner/_work/pavona/pavona/scratch/main/rv_timer-sim-vcs/2.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3279172583 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 3279172583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.rv_timer_stress_all_with_rand_reset.110079280361881563521019038005978508254515532898268041224785345594668055062428
Line 371, in log /home/runner/_work/pavona/pavona/scratch/main/rv_timer-sim-vcs/5.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5233361890 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 5233361890 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1171) [rv_timer_common_vseq] Check failed (vseq_done) has 2 failures:
6.rv_timer_stress_all_with_rand_reset.78300106206887859388809735399751142791947530528663668506448304716664338226373
Line 193, in log /home/runner/_work/pavona/pavona/scratch/main/rv_timer-sim-vcs/6.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 4572571580 ps: (cip_base_vseq.sv:1171) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
UVM_INFO @ 4572571580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.rv_timer_stress_all_with_rand_reset.70324636171790673607317470756215700102615933051422699146188860572858303987266
Line 327, in log /home/runner/_work/pavona/pavona/scratch/main/rv_timer-sim-vcs/12.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 1887147085 ps: (cip_base_vseq.sv:1171) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
UVM_INFO @ 1887147085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:346) [scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (* [*] vs * [*]) has 1 failures:
1.rv_timer_max.105367752227138978321323795169348782004129841796947990164967134723399281631391
Line 77, in log /home/runner/_work/pavona/pavona/scratch/main/rv_timer-sim-vcs/1.rv_timer_max/latest/run.log
UVM_ERROR @ 175660636 ps: (rv_timer_scoreboard.sv:346) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (0x0 [0] vs 0x1 [1])
UVM_INFO @ 175660636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---