SPI_DEVICE/1R1W Simulation Results

Saturday June 06 2026 03:15:30 UTC

GitHub Revision: 285e653a0b

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	5.158m	49.141ms	8	8	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.330s	226.079us	3	3	100.00
V1	csr_rw	spi_device_csr_rw	2.230s	382.003us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	22.000s	1.823ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	14.040s	1.883ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.050s	273.542us	4	4	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.230s	382.003us	20	20	100.00
		spi_device_csr_aliasing	14.040s	1.883ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.770s	36.714us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.560s	28.975us	3	3	100.00
V1		TOTAL			53	53	100.00
V2	csb_read	spi_device_csb_read	0.730s	82.303us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.820s	4.683us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.640s	5.881us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	0.930s	54.813us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	0.930s	54.813us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	1.920s	1.058ms	1	1	100.00
		spi_device_tpm_sts_read	0.810s	34.138us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	10.510s	4.057ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	6.860s	20.761ms	4	4	100.00
		spi_device_flash_all	4.639m	78.867ms	7	7	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	19.390s	27.171ms	4	4	100.00
		spi_device_flash_all	4.639m	78.867ms	7	7	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	19.390s	27.171ms	4	4	100.00
		spi_device_flash_all	4.639m	78.867ms	7	7	100.00
V2	cmd_info_slots	spi_device_flash_all	4.639m	78.867ms	7	7	100.00
V2	cmd_read_status	spi_device_intercept	13.290s	7.147ms	3	3	100.00
		spi_device_flash_all	4.639m	78.867ms	7	7	100.00
V2	cmd_read_jedec	spi_device_intercept	13.290s	7.147ms	3	3	100.00
		spi_device_flash_all	4.639m	78.867ms	7	7	100.00
V2	cmd_read_sfdp	spi_device_intercept	13.290s	7.147ms	3	3	100.00
		spi_device_flash_all	4.639m	78.867ms	7	7	100.00
V2	cmd_fast_read	spi_device_intercept	13.290s	7.147ms	3	3	100.00
		spi_device_flash_all	4.639m	78.867ms	7	7	100.00
V2	cmd_read_pipeline	spi_device_intercept	13.290s	7.147ms	3	3	100.00
		spi_device_flash_all	4.639m	78.867ms	7	7	100.00
V2	flash_cmd_upload	spi_device_upload	2.340s	457.949us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	1.820s	33.541us	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.820s	33.541us	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.820s	33.541us	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	21.440s	1.475ms	7	7	100.00
		spi_device_read_buffer_direct	2.660s	99.942us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.820s	33.541us	1	1	100.00
		spi_device_flash_all	4.639m	78.867ms	7	7	100.00
V2	quad_spi	spi_device_flash_all	4.639m	78.867ms	7	7	100.00
V2	dual_spi	spi_device_flash_all	4.639m	78.867ms	7	7	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	2.090s	198.485us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	2.090s	198.485us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	5.158m	49.141ms	8	8	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	5.550m	284.085ms	7	7	100.00
V2	stress_all	spi_device_stress_all	10.613m	509.509ms	18	18	100.00
V2	alert_test	spi_device_alert_test	0.810s	12.575us	3	3	100.00
V2	intr_test	spi_device_intr_test	0.870s	44.802us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.960s	1.944ms	5	5	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.960s	1.944ms	5	5	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.330s	226.079us	3	3	100.00
		spi_device_csr_rw	2.230s	382.003us	20	20	100.00
		spi_device_csr_aliasing	14.040s	1.883ms	5	5	100.00
		spi_device_same_csr_outstanding	2.880s	605.125us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.330s	226.079us	3	3	100.00
		spi_device_csr_rw	2.230s	382.003us	20	20	100.00
		spi_device_csr_aliasing	14.040s	1.883ms	5	5	100.00
		spi_device_same_csr_outstanding	2.880s	605.125us	20	20	100.00
V2		TOTAL			137	158	86.71
V2S	tl_intg_err	spi_device_sec_cm	1.180s	182.949us	3	3	100.00
		spi_device_tl_intg_err	18.940s	1.537ms	6	6	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	18.940s	1.537ms	6	6	100.00
V2S		TOTAL			9	9	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	4.609m	105.733ms	10	10	100.00
		TOTAL			209	230	90.87

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	8	8	8	100.00
V2	22	22	20	90.91
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.55	98.90	96.53	70.75	89.36	98.32	94.76	99.26

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 20 failures:
  • Test spi_device_mem_parity has 20 failures.

    • 0.spi_device_mem_parity.102944433984702067170229858055707854688937513067621537116998111299357817071692
      Line 83, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   4646502 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[92])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   4646502 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   4646502 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[988])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

    • 1.spi_device_mem_parity.16843684596370551887607218907850508033738015961345077610946547239187403312368
      Line 83, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   4682219 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[81])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   4682219 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   4682219 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[977])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

    • ... and 18 more failures.

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:
  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.112654886834677892009750264703135050754352856440280693461454255454112604342904
      Line 78, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   2842636 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x27b51 [100111101101010001] vs 0x0 [0])
        UVM_ERROR @   2932636 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3e978f [1111101001011110001111] vs 0x0 [0])
        UVM_ERROR @   3005636 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x903cac [100100000011110010101100] vs 0x0 [0])
        UVM_ERROR @   3076636 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x4322ff [10000110010001011111111] vs 0x0 [0])
        UVM_ERROR @   3153636 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xb5eccc [101101011110110011001100] vs 0x0 [0])