SPI_DEVICE/2P Simulation Results

Saturday June 06 2026 03:15:30 UTC

GitHub Revision: 285e653a0b

Branch: main

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_device_flash_and_tpm 5.357m 210.488ms 18 18 100.00
V1 csr_hw_reset spi_device_csr_hw_reset 1.120s 44.795us 3 3 100.00
V1 csr_rw spi_device_csr_rw 1.900s 409.568us 20 20 100.00
V1 csr_bit_bash spi_device_csr_bit_bash 19.590s 523.708us 5 5 100.00
V1 csr_aliasing spi_device_csr_aliasing 13.260s 4.111ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_device_csr_mem_rw_with_rand_reset 2.660s 2.294ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_device_csr_rw 1.900s 409.568us 20 20 100.00
spi_device_csr_aliasing 13.260s 4.111ms 5 5 100.00
V1 mem_walk spi_device_mem_walk 0.610s 22.602us 5 5 100.00
V1 mem_partial_access spi_device_mem_partial_access 1.670s 136.789us 5 5 100.00
V1 TOTAL 81 81 100.00
V2 csb_read spi_device_csb_read 0.840s 268.619us 1 1 100.00
V2 mem_parity spi_device_mem_parity 1.100s 33.058us 3 3 100.00
V2 mem_cfg spi_device_ram_cfg 0.870s 17.826us 3 3 100.00
V2 tpm_read spi_device_tpm_rw 0.800s 20.182us 1 1 100.00
V2 tpm_write spi_device_tpm_rw 0.800s 20.182us 1 1 100.00
V2 tpm_hw_reg spi_device_tpm_read_hw_reg 10.780s 8.690ms 1 1 100.00
spi_device_tpm_sts_read 0.910s 256.786us 1 1 100.00
V2 tpm_fully_random_case spi_device_tpm_all 25.220s 6.270ms 4 4 100.00
V2 pass_cmd_filtering spi_device_pass_cmd_filtering 5.150s 639.341us 1 1 100.00
spi_device_flash_all 3.982m 114.770ms 7 7 100.00
V2 pass_addr_translation spi_device_pass_addr_payload_swap 17.790s 5.493ms 3 3 100.00
spi_device_flash_all 3.982m 114.770ms 7 7 100.00
V2 pass_payload_translation spi_device_pass_addr_payload_swap 17.790s 5.493ms 3 3 100.00
spi_device_flash_all 3.982m 114.770ms 7 7 100.00
V2 cmd_info_slots spi_device_flash_all 3.982m 114.770ms 7 7 100.00
V2 cmd_read_status spi_device_intercept 2.210s 108.104us 1 1 100.00
spi_device_flash_all 3.982m 114.770ms 7 7 100.00
V2 cmd_read_jedec spi_device_intercept 2.210s 108.104us 1 1 100.00
spi_device_flash_all 3.982m 114.770ms 7 7 100.00
V2 cmd_read_sfdp spi_device_intercept 2.210s 108.104us 1 1 100.00
spi_device_flash_all 3.982m 114.770ms 7 7 100.00
V2 cmd_fast_read spi_device_intercept 2.210s 108.104us 1 1 100.00
spi_device_flash_all 3.982m 114.770ms 7 7 100.00
V2 cmd_read_pipeline spi_device_intercept 2.210s 108.104us 1 1 100.00
spi_device_flash_all 3.982m 114.770ms 7 7 100.00
V2 flash_cmd_upload spi_device_upload 10.280s 3.884ms 1 1 100.00
V2 mailbox_command spi_device_mailbox 1.669m 31.645ms 1 1 100.00
V2 mailbox_cross_outside_command spi_device_mailbox 1.669m 31.645ms 1 1 100.00
V2 mailbox_cross_inside_command spi_device_mailbox 1.669m 31.645ms 1 1 100.00
V2 cmd_read_buffer spi_device_flash_mode 35.050s 10.510ms 7 7 100.00
spi_device_read_buffer_direct 5.850s 2.558ms 1 1 100.00
V2 cmd_dummy_cycle spi_device_mailbox 1.669m 31.645ms 1 1 100.00
spi_device_flash_all 3.982m 114.770ms 7 7 100.00
V2 quad_spi spi_device_flash_all 3.982m 114.770ms 7 7 100.00
V2 dual_spi spi_device_flash_all 3.982m 114.770ms 7 7 100.00
V2 4b_3b_feature spi_device_cfg_cmd 4.000s 581.405us 4 4 100.00
V2 write_enable_disable spi_device_cfg_cmd 4.000s 581.405us 4 4 100.00
V2 TPM_with_flash_or_passthrough_mode spi_device_flash_and_tpm 5.357m 210.488ms 18 18 100.00
V2 tpm_and_flash_trans_with_min_inactive_time spi_device_flash_and_tpm_min_idle 2.757m 41.433ms 9 9 100.00
V2 stress_all spi_device_stress_all 7.688m 947.442ms 11 11 100.00
V2 alert_test spi_device_alert_test 0.880s 21.649us 3 3 100.00
V2 intr_test spi_device_intr_test 0.670s 27.133us 50 50 100.00
V2 tl_d_oob_addr_access spi_device_tl_errors 3.910s 410.625us 6 6 100.00
V2 tl_d_illegal_access spi_device_tl_errors 3.910s 410.625us 6 6 100.00
V2 tl_d_outstanding_access spi_device_csr_hw_reset 1.120s 44.795us 3 3 100.00
spi_device_csr_rw 1.900s 409.568us 20 20 100.00
spi_device_csr_aliasing 13.260s 4.111ms 5 5 100.00
spi_device_same_csr_outstanding 2.410s 458.551us 3 3 100.00
V2 tl_d_partial_access spi_device_csr_hw_reset 1.120s 44.795us 3 3 100.00
spi_device_csr_rw 1.900s 409.568us 20 20 100.00
spi_device_csr_aliasing 13.260s 4.111ms 5 5 100.00
spi_device_same_csr_outstanding 2.410s 458.551us 3 3 100.00
V2 TOTAL 122 122 100.00
V2S tl_intg_err spi_device_sec_cm 1.600s 961.875us 3 3 100.00
spi_device_tl_intg_err 14.260s 915.108us 7 7 100.00
V2S sec_cm_bus_integrity spi_device_tl_intg_err 14.260s 915.108us 7 7 100.00
V2S TOTAL 10 10 100.00
V3 stress_all_with_rand_reset spi_device_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
Unmapped tests spi_device_flash_mode_ignore_cmds 4.220m 163.550ms 8 8 100.00
TOTAL 221 221 100.00

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 1 100.00
V1 8 8 8 100.00
V2 22 22 22 100.00
V2S 2 2 2 100.00
V3 1 0 0 0.00

Coverage Results

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
93.14 98.96 96.63 74.63 89.36 98.40 94.74 99.26