SPI_HOST Simulation Results

Saturday June 06 2026 03:15:30 UTC

GitHub Revision: 285e653a0b

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	1.777m	4.690ms	50	50	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	0.680s	19.866us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	0.670s	49.106us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	1.420s	526.833us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	0.730s	45.106us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	1.120s	55.972us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	0.670s	49.106us	20	20	100.00
		spi_host_csr_aliasing	0.730s	45.106us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	0.690s	16.318us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	0.670s	23.809us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	performance	spi_host_performance	1.310s	97.511us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	1.209m	5.221ms	50	50	100.00
		spi_host_error_cmd	0.780s	17.801us	50	50	100.00
		spi_host_event	10.289m	32.325ms	50	50	100.00
V2	clock_rate	spi_host_speed	13.830s	1.852ms	50	50	100.00
V2	speed	spi_host_speed	13.830s	1.852ms	50	50	100.00
V2	chip_select_timing	spi_host_speed	13.830s	1.852ms	50	50	100.00
V2	sw_reset	spi_host_sw_reset	1.227m	3.556ms	45	50	90.00
V2	passthrough_mode	spi_host_passthrough_mode	0.770s	68.385us	50	50	100.00
V2	cpol_cpha	spi_host_speed	13.830s	1.852ms	50	50	100.00
V2	full_cycle	spi_host_speed	13.830s	1.852ms	50	50	100.00
V2	duplex	spi_host_smoke	1.777m	4.690ms	50	50	100.00
V2	tx_rx_only	spi_host_smoke	1.777m	4.690ms	50	50	100.00
V2	stress_all	spi_host_stress_all	1.968m	19.517ms	50	50	100.00
V2	spien	spi_host_spien	2.463m	41.615ms	49	50	98.00
V2	stall	spi_host_status_stall	5.075m	11.109ms	48	50	96.00
V2	Idlecsbactive	spi_host_idlecsbactive	27.160s	10.682ms	50	50	100.00
V2	data_fifo_status	spi_host_overflow_underflow	1.209m	5.221ms	50	50	100.00
V2	alert_test	spi_host_alert_test	0.740s	49.343us	50	50	100.00
V2	intr_test	spi_host_intr_test	0.620s	51.189us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	1.670s	500.044us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	1.670s	500.044us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	0.680s	19.866us	5	5	100.00
		spi_host_csr_rw	0.670s	49.106us	20	20	100.00
		spi_host_csr_aliasing	0.730s	45.106us	5	5	100.00
		spi_host_same_csr_outstanding	0.860s	35.134us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	0.680s	19.866us	5	5	100.00
		spi_host_csr_rw	0.670s	49.106us	20	20	100.00
		spi_host_csr_aliasing	0.730s	45.106us	5	5	100.00
		spi_host_same_csr_outstanding	0.860s	35.134us	20	20	100.00
V2		TOTAL			682	690	98.84
V2S	tl_intg_err	spi_host_tl_intg_err	1.060s	81.890us	20	20	100.00
		spi_host_sec_cm	0.910s	140.754us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	1.060s	81.890us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	winbond	winbond			0	0	--
V3	stress_all_with_rand_reset	spi_host_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
	Unmapped tests	spi_host_upper_range_clkdiv	52.206m	195.567ms	3	10	30.00
		TOTAL			825	840	98.21

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	8	8	8	100.00
V2	15	15	12	80.00
V2S	2	2	2	100.00
V3	2	0	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.15	97.51	90.25	74.60	88.24	92.16	95.64	85.68

Failure Buckets

• UVM_FATAL (spi_host_base_vseq.sv:233) virtual_sequencer [spi_host_env_pkg::\spi_host_base_vseq::stoppable_timeout ()] timeout = *ns spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=* has 4 failures:

  • Test spi_host_upper_range_clkdiv has 4 failures.

    • 0.spi_host_upper_range_clkdiv.2166847455053359353172620144263489315174237198769945906525496230654335628080
      Line 153, in log /home/runner/_work/pavona/pavona/scratch/main/spi_host-sim-vcs/0.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 50001261628 ps: (spi_host_base_vseq.sv:233) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::\spi_host_base_vseq::stoppable_timeout ()] timeout = 50000000ns spi_host_reg_block.status.rxempty (addr=0x4f19c9d4, Comparison=CompareOpEq, exp_data=0x0, call_count=6
        UVM_INFO @ 50001261628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.spi_host_upper_range_clkdiv.101740756891696711282374956257128397105050085112463199852340827968219150660907
      Line 118, in log /home/runner/_work/pavona/pavona/scratch/main/spi_host-sim-vcs/1.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 50007971822 ps: (spi_host_base_vseq.sv:233) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::\spi_host_base_vseq::stoppable_timeout ()] timeout = 50000000ns spi_host_reg_block.status.rxempty (addr=0x59bccd94, Comparison=CompareOpEq, exp_data=0x0, call_count=6
        UVM_INFO @ 50007971822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 2 more failures.

• UVM_FATAL (spi_host_base_vseq.sv:227) virtual_sequencer [spi_host_env_pkg::\spi_host_base_vseq::stoppable_timeout .unnamed$$_*] Event has already been triggered with stop=* has 4 failures:

  • Test spi_host_sw_reset has 4 failures.

    • 23.spi_host_sw_reset.106148617012429856546786412177766019966653347137417397215677058827049802140233
      Line 352, in log /home/runner/_work/pavona/pavona/scratch/main/spi_host-sim-vcs/23.spi_host_sw_reset/latest/run.log

        UVM_FATAL @ 470189087 ps: (spi_host_base_vseq.sv:227) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::\spi_host_base_vseq::stoppable_timeout .unnamed$$_0] Event has already been triggered with stop=1
        UVM_INFO @ 470189087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 32.spi_host_sw_reset.18506323459044437153447103717953029040413014925086284382388398155188465765612
      Line 194, in log /home/runner/_work/pavona/pavona/scratch/main/spi_host-sim-vcs/32.spi_host_sw_reset/latest/run.log

        UVM_FATAL @ 220966184 ps: (spi_host_base_vseq.sv:227) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::\spi_host_base_vseq::stoppable_timeout .unnamed$$_0] Event has already been triggered with stop=1
        UVM_INFO @ 220966184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 2 more failures.

• UVM_FATAL (spi_host_base_vseq.sv:233) virtual_sequencer [spi_host_env_pkg::\spi_host_base_vseq::stoppable_timeout ()] timeout = *ns spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=* has 3 failures:

  • Test spi_host_upper_range_clkdiv has 3 failures.

    • 2.spi_host_upper_range_clkdiv.36914973993206010842568424397441331929231470668673812184082478061431427328172
      Line 147, in log /home/runner/_work/pavona/pavona/scratch/main/spi_host-sim-vcs/2.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 100011664419 ps: (spi_host_base_vseq.sv:233) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::\spi_host_base_vseq::stoppable_timeout ()] timeout = 100000000ns spi_host_reg_block.status.active (addr=0x251a2a54, Comparison=CompareOpEq, exp_data=0x0, call_count=14
        UVM_INFO @ 100011664419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 5.spi_host_upper_range_clkdiv.17389523189926590239201894255041859956609270845282646115204075948555660324197
      Line 133, in log /home/runner/_work/pavona/pavona/scratch/main/spi_host-sim-vcs/5.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 100002223117 ps: (spi_host_base_vseq.sv:233) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::\spi_host_base_vseq::stoppable_timeout ()] timeout = 100000000ns spi_host_reg_block.status.active (addr=0x304dbd14, Comparison=CompareOpEq, exp_data=0x0, call_count=10
        UVM_INFO @ 100002223117 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• Offending '(!$changed(signal2check_i[*]))' has 1 failures:

  • Test spi_host_status_stall has 1 failures.

    • 6.spi_host_status_stall.108398378219804088296896609699841988461327353460860340019302952687051014408338
      Line 843, in log /home/runner/_work/pavona/pavona/scratch/main/spi_host-sim-vcs/6.spi_host_status_stall/latest/run.log

            Offending '(!$changed(signal2check_i[1]))'
        UVM_ERROR @ 1051736317 ps: [NEGEDGE_SAME_VALUE_CHECK_P] tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1].NEGEDGE_SAME_VALUE_CHECK_P: [i=1] - ASSERTION FAILED pos_value (0x0) != neg_value (0x0) - time=1051736000 ps
        UVM_INFO @ 1051736317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (spi_host_scoreboard.sv:220) scoreboard [scoreboard] 'rx_data_q.size' is empty - hence can't compare TXN has 1 failures:

  • Test spi_host_sw_reset has 1 failures.

    • 13.spi_host_sw_reset.80436083257365032592824886048132925597748811471979572323695475853725073591019
      Line 210, in log /home/runner/_work/pavona/pavona/scratch/main/spi_host-sim-vcs/13.spi_host_sw_reset/latest/run.log

        UVM_FATAL @   7800458 ps: (spi_host_scoreboard.sv:220) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] 'rx_data_q.size' is empty - hence can't compare TXN
        UVM_INFO @   7800458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (spi_host_base_vseq.sv:233) virtual_sequencer [spi_host_env_pkg::\spi_host_base_vseq::stoppable_timeout ()] timeout = *ns spi_host_reg_block.status.rxqd (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=* has 1 failures:

  • Test spi_host_spien has 1 failures.

    • 19.spi_host_spien.71200404403818128764131844571399127405854507265120749614110792410712803027475
      Line 325, in log /home/runner/_work/pavona/pavona/scratch/main/spi_host-sim-vcs/19.spi_host_spien/latest/run.log

        UVM_FATAL @ 10825691921 ps: (spi_host_base_vseq.sv:233) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::\spi_host_base_vseq::stoppable_timeout ()] timeout = 10000000ns spi_host_reg_block.status.rxqd (addr=0x3a3cfbd4, Comparison=CompareOpEq, exp_data=0x0, call_count=64
        UVM_INFO @ 10825691921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test spi_host_status_stall has 1 failures.

    • 23.spi_host_status_stall.97998810890468109656491802887787606016116309862658770649752605220183403412559
      Line 1483, in log /home/runner/_work/pavona/pavona/scratch/main/spi_host-sim-vcs/23.spi_host_status_stall/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---