SRAM_CTRL/EXEC_64KB Simulation Results

Saturday June 06 2026 03:15:30 UTC

GitHub Revision: 285e653a0b

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	23.660s	1.942ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.740s	18.432us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.660s	13.040us	3	3	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.410s	174.757us	3	3	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.670s	13.570us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.670s	746.331us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.660s	13.040us	3	3	100.00
		sram_ctrl_csr_aliasing	0.670s	13.570us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	47.770s	2.937ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.042m	1.263ms	1	1	100.00
V1		TOTAL			39	39	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	1.627m	1.992ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.230m	12.417ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	8.226m	42.758ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	15.890m	154.946ms	3	3	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	22.330s	25.601ms	1	1	100.00
V2	executable	sram_ctrl_executable	7.707m	8.830ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	1.666m	770.285us	1	1	100.00
		sram_ctrl_partial_access_b2b	6.486m	24.185ms	4	4	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.180m	685.815us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	1.471m	4.474ms	1	1	100.00
		sram_ctrl_throughput_w_readback	1.664m	2.546ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	18.412m	206.015ms	4	4	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.130s	236.532us	3	3	100.00
V2	stress_all	sram_ctrl_stress_all	1.914h	325.478ms	6	6	100.00
V2	alert_test	sram_ctrl_alert_test	0.790s	36.881us	3	3	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.000s	2.198ms	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.000s	2.198ms	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.740s	18.432us	5	5	100.00
		sram_ctrl_csr_rw	0.660s	13.040us	3	3	100.00
		sram_ctrl_csr_aliasing	0.670s	13.570us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.710s	70.007us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.740s	18.432us	5	5	100.00
		sram_ctrl_csr_rw	0.660s	13.040us	3	3	100.00
		sram_ctrl_csr_aliasing	0.670s	13.570us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.710s	70.007us	20	20	100.00
V2		TOTAL			72	72	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	12.290s	7.334ms	3	3	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	4.360s	1.363ms	3	3	100.00
		sram_ctrl_tl_intg_err	1.840s	1.461ms	7	7	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	4.360s	1.363ms	3	3	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.840s	1.461ms	7	7	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	18.412m	206.015ms	4	4	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	18.412m	206.015ms	4	4	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.660s	13.040us	3	3	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	7.707m	8.830ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	7.707m	8.830ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	7.707m	8.830ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	22.330s	25.601ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	3.650s	2.785ms	4	4	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	12.290s	7.334ms	3	3	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	3.810s	1.678ms	3	3	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	23.660s	1.942ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	23.660s	1.942ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	7.707m	8.830ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	4.360s	1.363ms	3	3	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	22.330s	25.601ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	4.360s	1.363ms	3	3	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	4.360s	1.363ms	3	3	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	23.660s	1.942ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	4.360s	1.363ms	3	3	100.00
V2S		TOTAL			20	20	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	2.280m	3.396ms	4	4	100.00
V3		TOTAL			4	4	100.00
		TOTAL			135	135	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	17	17	17	100.00
V2S	5	5	5	100.00
V3	1	1	1	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.30	99.29	96.45	91.26	100.00	99.01	96.38	98.70