SRAM_CTRL/MAIN Simulation Results

Saturday June 06 2026 03:15:30 UTC

GitHub Revision: 285e653a0b

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	10.020s	966.447us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.810s	46.901us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.820s	44.184us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.660s	124.296us	3	3	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.810s	106.749us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	4.370s	1.431ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.820s	44.184us	20	20	100.00
		sram_ctrl_csr_aliasing	0.810s	106.749us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	2.650m	17.907ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	48.680s	2.886ms	1	1	100.00
V1		TOTAL			56	56	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	22.626m	47.239ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.496m	5.520ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	11.276m	178.519ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	16.160m	61.471ms	3	3	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	26.430s	10.052ms	1	1	100.00
V2	executable	sram_ctrl_executable	15.835m	60.100ms	4	4	100.00
V2	partial_access	sram_ctrl_partial_access	9.220s	3.355ms	1	1	100.00
		sram_ctrl_partial_access_b2b	4.744m	101.259ms	3	3	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.274m	785.930us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	30.690s	734.753us	1	1	100.00
		sram_ctrl_throughput_w_readback	1.713m	1.872ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	15.227m	3.196ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.740s	691.886us	3	3	100.00
V2	stress_all	sram_ctrl_stress_all	1.103h	360.855ms	5	5	100.00
V2	alert_test	sram_ctrl_alert_test	0.770s	47.184us	3	3	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.400s	497.568us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.400s	497.568us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.810s	46.901us	5	5	100.00
		sram_ctrl_csr_rw	0.820s	44.184us	20	20	100.00
		sram_ctrl_csr_aliasing	0.810s	106.749us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.920s	70.595us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.810s	46.901us	5	5	100.00
		sram_ctrl_csr_rw	0.820s	44.184us	20	20	100.00
		sram_ctrl_csr_aliasing	0.810s	106.749us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.920s	70.595us	20	20	100.00
V2		TOTAL			70	70	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	29.380s	12.856ms	4	4	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	5.540s	1.067ms	4	4	100.00
		sram_ctrl_tl_intg_err	2.970s	3.769ms	8	8	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	5.540s	1.067ms	4	4	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.970s	3.769ms	8	8	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	15.227m	3.196ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	15.227m	3.196ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.820s	44.184us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	15.835m	60.100ms	4	4	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	15.835m	60.100ms	4	4	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	15.835m	60.100ms	4	4	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	26.430s	10.052ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	6.400s	11.028ms	4	4	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	29.380s	12.856ms	4	4	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	5.240s	3.664ms	3	4	75.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	10.020s	966.447us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	10.020s	966.447us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	15.835m	60.100ms	4	4	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	5.540s	1.067ms	4	4	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	26.430s	10.052ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	5.540s	1.067ms	4	4	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	5.540s	1.067ms	4	4	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	10.020s	966.447us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	5.540s	1.067ms	4	4	100.00
V2S		TOTAL			23	24	95.83
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	45.770s	3.098ms	6	6	100.00
V3		TOTAL			6	6	100.00
		TOTAL			155	156	99.36

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	17	17	17	100.00
V2S	5	5	4	80.00
V3	1	1	1	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.56	99.29	96.45	85.92	100.00	99.01	96.38	98.89

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 1 failures:
  • Test sram_ctrl_readback_err has 1 failures.

    • 2.sram_ctrl_readback_err.23960020192356685965958647523584280496599651423141417335922686548036602237395
      Line 107, in log /home/runner/_work/pavona/pavona/scratch/main/sram_ctrl_main-sim-vcs/2.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 3287024110 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x58) != exp (0x41)
        UVM_INFO @ 3287024110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---